參數(shù)資料
型號： SMJ320C6201BGLE
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： DIGITAL SIGNAL PROCESSORS
中文描述： 數(shù)字信號處理器
文件頁數(shù)： 57/73頁
文件大小： 1093K
代理商： SMJ320C6201BGLE
SM320C6201, SMJ320C6201B
DIGITAL SIGNAL PROCESSORS
SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999
57
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0
(see Figure 34)
(’C6201)
’C6201-150
NO.
MASTER
MIN
SLAVE
MIN
UNIT
MAX
MAX
4
tsu(DRV-CKXL)
th(CKXL-DRV)
Setup time, DR valid before CLKX low
12
3P – 2*
ns
5
Hold time, DR valid after CLKX low
4*
5 + 6P
ns
The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency
in ns. For example, when running parts at 150 MHz, use P = 6.67 ns.
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
*This parameter is not production tested.
switching characteristics for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0
(see Figure 34) (’C6201)
’C6201-150
NO.
PARAMETER
MASTER§
MIN
SLAVE
MIN
UNIT
MAX
MAX
1
th(CKXL-FXL)
td(FXL-CKXH)
Hold time, FSX low after CLKX low
Delay time, FSX low to CLKX high#
T – 2*
T + 3*
ns
2
L – 2*
L + 3*
ns
3
td(CKXH-DXV)
Delay time, CLKX high to DX valid
This is also specified by design but not tested to be the delay
time for data to be low impedance on the first data bit.
–2*
4*
3P + 4*
5P + 17*
ns
6
tdis(CKXL-DXHZ)
Disable time, DX high impedance following last data bit from
CLKX low
L – 2*
L + 3*
ns
7
tdis(FXH-DXHZ)
Disable time, DX high impedance following last data bit from
FSX high
P + 4*
3P + 17*
ns
8
td(FXL-DXV)
Delay time, FSX low to DX valid
2P + 4*
4P + 17
ns
The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency
in ns. For example, when running parts at 150 MHz, use P = 6.67 ns.
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
§T =
CLKX period = (1 + CLKGDV) * P; if CLKSM = 1, then P = 1/CPU clock frequency
=
CLKX period = (1 + CLKGDV) * P_clks; if CLKSM = 0, then P_clks = CLKS period.
H =
CLKX high pulse width = (CLKGDV/2 + 1) * T
L =
CLKX low pulse width = (CLKGDV/2) * T
FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
*This parameter is not production tested.
#FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
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