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參數(shù)資料
| 型號(hào)： | SMJ320C6201BGLE |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | DIGITAL SIGNAL PROCESSORS |
| 中文描述： | 數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 53/73頁(yè) |
| 文件大?。?/td> | 1093K |
| 代理商： | SMJ320C6201BGLE |
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SM320C6201, SMJ320C6201B
DIGITAL SIGNAL PROCESSORS
SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999
53
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING
timing requirements for McBSP
(see Figure 32)
NO.
’C6201-150
’C6201B-150
’C6201B-200
UNIT
MIN
MAX
MIN
MAX
2
tc(CKRX)
Cycle time, CLKR/X
CLKR/X ext
2*
2
CLKOUT1
cycles
3
tw(CKRX)
Pulse duration, CLKR/X high or CLKR/X
low
CLKR/X ext
P – 1*
P – 1
ns
5
tsu(FRH-CKRL)
(FRH CKRL)
Setup time, external FSR high before
CLKR low
CLKR int
13
9
ns
CLKR ext
4
1
6
th(CKRL FRH)
th(CKRL-FRH)
Hold time, external FSR high after CLKR
low
CLKR int
7*
6
ns
CLKR ext
3.5
3
7
tsu(DRV-CKRL)
(DRV CKRL)
Setup time DR valid before CLKR low
Setup time, DR valid before CLKR low
CLKR int
13.5
8
ns
CLKR ext
1
0
8
th(CKRL DRV)
th(CKRL-DRV)
Hold time DR valid after CLKR low
Hold time, DR valid after CLKR low
CLKR int
4*
3
ns
CLKR ext
4
3
10
tsu(FXH-CKXL)
(FXH CKXL)
Setup time, external FSX high before
CLKX low
CLKX int
13
9
ns
CLKX ext
4
1
11
th(CKXL FXH)
th(CKXL-FXH)
Hold time, external FSX high after CLKX
low
CLKX int
CLKX ext
7
6
3
ns
3.5
CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter or SSCLK duty cycle.
P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.67 ns.
*This parameter is not production tested.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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