參數(shù)資料
型號: SMJ320C6201BGLE
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號處理
英文描述: DIGITAL SIGNAL PROCESSORS
中文描述: 數(shù)字信號處理器
文件頁數(shù): 49/73頁
文件大小: 1093K
代理商: SMJ320C6201BGLE
SM320C6201, SMJ320C6201B
DIGITAL SIGNAL PROCESSORS
SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999
49
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
EXTERNAL INTERRUPT/RESET TIMING
timing requirements for interrupt response cycles
(see Figure 27)
NO.
’C6201-150
’C6201B-150
’C6201B-200
UNIT
MIN
MAX
MIN
MAX
3
tw(ILOW)
Width of the interrupt pulse low
2
2
CLKOUT1
cycles
4
tw(IHIGH)
Width of the interrupt pulse high
2
2
CLKOUT1
cycles
Interrupt signals are synchronized internally and are potentially recognized one cycle later if setup and hold times are violated. Thus, they can
be connected to asynchronous inputs.
switching characteristics during interrupt response cycles (see Figure 27)
NO.
PARAMETER
’C6201-150
’C6201B-150
’C6201B-200
UNIT
MIN
MAX
MIN
MAX
1
tR(EINTH-IACKH)
Response time, EXT_INTx high to IACK high
9*
9
CLKOUT1
cycles
2
tR(ISFP)
Response time, interrupt service fetch packet execution after
EXT_INTx high
11*
11
CLKOUT1
cycles
5
td(CKO2L-IACKV)
td(CKO2L-INUMV)
td(CKO2L-INUMIV)
Add two CLKOUT1 cycles to this parameter if the interrupt is recognized during the high half of CLKOUT2
*This parameter is not production tested.
Delay time, CLKOUT2 low to IACK valid
0*
10
0
10
ns
6
Delay time, CLKOUT2 low to INUMx valid
0*
10
0
10
ns
7
Delay time, CLKOUT2 low to INUMx invalid
0*
10*
0
10
ns
1
2
3
4
5
PG
PS PW
PR
DP
DC
E1
Interrupt Number
7
6
5
5
4
3
1
2
CLKOUT1
EXT_INTx, NMI
Interrupt Flag
IACK
INUMx
CLKOUT2
Figure 27. Interrupt Timing
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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