參數(shù)資料
型號： SMJ320C6201BGLE
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： DIGITAL SIGNAL PROCESSORS
中文描述： 數(shù)字信號處理器
文件頁數(shù)： 42/73頁
文件大小： 1093K
代理商： SMJ320C6201BGLE
SM320C6201, SMJ320C6201B
DIGITAL SIGNAL PROCESSORS
SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999
42
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
SYNCHRONOUS DRAM TIMING (CONTINUED)
timing requirements for synchronous DRAM cycles (see Figure 19) (’C6201B)
NO.
’C6201B-150
MIN
’C6201B-200
MIN
UNIT
MAX
MAX
7
tsu(EDV-SDCLKH)
th(SDCLKH-EDV)
Setup time, read EDx valid before SDCLK high
1.5
1
ns
8
Hold time, read EDx valid after SDCLK high
3
3
ns
switching characteristics for synchronous DRAM cycles
(see Figure 19–Figure 24) (’C6201B)
NO.
PARAMETER
’C6201B-150
MIN
’C6201B-200
MIN
UNIT
MAX
MAX
1
tsu(CEV-SDCLKH)
Setup time, CEx valid
before SDCLK high
1.5P – 6
1.5P – 3.5
ns
2
toh(SDCLKH-CEV)
Output hold time, CEx valid after SDCLK high
0.5P – 2
0.5P – 1
ns
3
tsu(BEV-SDCLKH)
Setup time, BEx valid
before SDCLK high
1.5P – 6
1.5P – 3.5
ns
4
toh(SDCLKH-BEIV)
Output hold time, BEx
invalid after SDCLK high
0.5P – 2
0.5P – 1
ns
5
tsu(EAV-SDCLKH)
Setup time, EAx valid
before SDCLK high
1.5P – 6
1.5P – 3.5
ns
6
toh(SDCLKH-EAIV)
Output hold time, EAx
invalid after SDCLK high
0.5P – 2
0.5P – 1
ns
9
tsu(SDCAS-SDCLKH)
Setup time, SDCAS valid
before SDCLK high
1.5P – 6
1.5P – 3.5
ns
10
toh(SDCLKH-SDCAS)
Output hold time, SDCAS valid after SDCLK high
0.5P – 2
0.5P – 1
ns
11
tsu(EDV-SDCLKH)
Setup time, EDx valid
before SDCLK high
1.5P – 6
1.5P – 3.5
ns
12
toh(SDCLKH-EDIV)
Output hold time, EDx
invalid after SDCLK high
0.5P – 2
0.5P – 1
ns
13
tsu(SDWE-SDCLKH)
Setup time, SDWE valid
before SDCLK high
1.5P – 6
1.5P – 3.5
ns
14
toh(SDCLKH-SDWE)
Output hold time, SDWE valid after SDCLK high
0.5P – 2
0.5P – 1
ns
15
tsu(SDA10V-SDCLKH)
Setup time, SDA10 valid
before SDCLK high
1.5P – 6
1.5P – 3.5
ns
16
toh(SDCLKH-SDA10IV)
Output hold time, SDA10 invalid after SDCLK
high
0.5P – 2
0.5P – 1
ns
17
tsu(SDRAS-SDCLKH)
Setup time, SDRAS valid
before SDCLK high
1.5P – 6
1.5P – 3.5
ns
18
toh(SDCLKH-SDRAS)
The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter or SDCLK duty cycle.
P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.67 ns.
Output hold time, SDRAS valid after SDCLK high
0.5P – 2
0.5P – 1
ns
P
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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