參數(shù)資料
型號(hào)： SMJ320C6201BGLE
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： DIGITAL SIGNAL PROCESSORS
中文描述： 數(shù)字信號(hào)處理器
文件頁數(shù)： 41/73頁
文件大?。?/td> 1093K
代理商： SMJ320C6201BGLE
SM320C6201, SMJ320C6201B
DIGITAL SIGNAL PROCESSORS
SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999
41
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
SYNCHRONOUS DRAM TIMING
timing requirements for synchronous DRAM cycles (see Figure 19) (’C6201)
NO.
’C6201-150
MIN
UNIT
MAX
7
tsu(EDV-SDCLKH)
th(SDCLKH-EDV)
Setup time, read EDx valid before SDCLK high
3.5
ns
8
Hold time, read EDx valid after SDCLK high
1.2
ns
switching characteristics for synchronous DRAM cycles
(see Figure 19–Figure 24) (’C6201)
NO.
PARAMETER
’C6201-150
MIN
UNIT
MAX
1
tsu(CEV-SDCLKH)
toh(SDCLKH-CEV)
tsu(BEV-SDCLKH)
toh(SDCLKH-BEIV)
tsu(EAV-SDCLKH)
toh(SDCLKH-EAIV)
tsu(SDCAS-SDCLKH)
toh(SDCLKH-SDCAS)
tsu(EDV-SDCLKH)
toh(SDCLKH-EDIV)
tsu(SDWE-SDCLKH)
toh(SDCLKH-SDWE)
tsu(SDA10V-SDCLKH)
toh(SDCLKH-SDA10IV)
tsu(SDRAS-SDCLKH)
toh(SDCLKH-SDRAS)
The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter or SDCLK duty cycle.
P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.67 ns.
*This parameter is not production tested.
Setup time, CEx valid before SDCLK high
P – 4.2
ns
2
Output hold time, CEx valid after SDCLK high
P – 5.2
ns
3
Setup time, BEx valid before SDCLK high
P – 4.2
ns
4
Output hold time, BEx invalid after SDCLK high
P – 5.2*
ns
5
Setup time, EAx valid before SDCLK high
P – 4.2
ns
6
Output hold time, EAx invalid after SDCLK high
P – 5.2*
ns
9
Setup time, SDCAS valid before SDCLK high
P – 4.2
ns
10
Output hold time, SDCAS valid after SDCLK high
P – 5.2
ns
11
Setup time, EDx valid before SDCLK high
P – 4.2*
ns
12
Output hold time, EDx invalid after SDCLK high
P – 5.2*
ns
13
Setup time, SDWE valid before SDCLK high
P – 4.2
ns
14
Output hold time, SDWE valid after SDCLK high
P – 5.2
ns
15
Setup time, SDA10 valid before SDCLK high
P – 4.2
ns
16
Output hold time, SDA10 invalid after SDCLK high
P – 5.2*
ns
17
Setup time, SDRAS valid before SDCLK high
P – 4.2
ns
18
Output hold time, SDRAS valid after SDCLK high
P – 5.2
ns
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