參數(shù)資料
型號(hào)： SMJ320C6201BGLE
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： DIGITAL SIGNAL PROCESSORS
中文描述： 數(shù)字信號(hào)處理器
文件頁數(shù)： 39/73頁
文件大?。?/td> 1093K
代理商： SMJ320C6201BGLE
SM320C6201, SMJ320C6201B
DIGITAL SIGNAL PROCESSORS
SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999
39
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)
timing requirements for synchronous-burst SRAM cycles (half-rate SSCLK)
(see Figure 17) (’C6201B)
NO.
’C6201B-150
MIN
’C6201B-200
MIN
UNIT
MAX
MAX
7
tsu(EDV-SSCLKH)
th(SSCLKH-EDV)
Setup time, read EDx valid before SSCLK high
4.2
2.5
ns
8
Hold time, read EDx valid after SSCLK high
1.5
1.5
ns
switching characteristics for synchronous-burst SRAM cycles
(half-rate SSCLK)
(see Figure 17 and Figure 18) (’C6201B)
NO.
PARAMETER
’C6201B-150
MIN
’C6201B-200
MIN
UNIT
MAX
MAX
1
tsu(CEV-SSCLKH)
Setup time, CEx
valid before SSCLK high
1.5P – 5.5
1.5P – 3
ns
2
toh(SSCLKH-CEV)
Output hold time, CEx valid
after SSCLK high
0.5P – 2.4
0.5P – 1.5
ns
3
tsu(BEV-SSCLKH)
Setup time, BEx
valid before SSCLK high
1.5P – 5.5
1.5P – 3
ns
4
toh(SSCLKH-BEIV)
Output hold time, BEx invalid after SSCLK high
0.5P – 2.4
0.5P – 1.5
ns
5
tsu(EAV-SSCLKH)
Setup time, EAx
valid before SSCLK high
1.5P – 5.5
1.5P – 3
ns
6
toh(SSCLKH-EAIV)
Output hold time, EAx invalid after SSCLK high
0.5P – 2.4
0.5P – 1.5
ns
9
tsu(ADSV-SSCLKH)
Setup time, SSADS valid
before SSCLK high
1.5P – 5.5
1.5P – 3
ns
10
toh(SSCLKH-ADSV)
tsu(OEV-SSCLKH)
toh(SSCLKH-OEV)
tsu(EDV-SSCLKH)
toh(SSCLKH-EDIV)
tsu(WEV-SSCLKH)
toh(SSCLKH-WEV)
The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter or SSCLK duty cycle.
P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.67 ns.
Output hold time, SSADS valid after SSCLK high
0.5P – 2.4
0.5P – 1.5
ns
11
Setup time, SSOE valid before SSCLK high
1.5P – 5.5
1.5P – 3
ns
12
Output hold time, SSOE valid after SSCLK high
0.5P – 2.4
0.5P – 1.5
ns
13
Setup time, EDx valid before SSCLK high
1.5P – 5.5
1.5P – 3
ns
14
Output hold time, EDx invalid after SSCLK high
0.5P – 2.4
0.5P – 1.5
ns
15
Setup time, SSWE valid before SSCLK high
1.5P – 5.5
1.5P – 3
ns
16
Output hold time, SSWE valid after SSCLK high
0.5P – 2.4
0.5P – 1.5
ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
P
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