參數(shù)資料
型號： SMJ320C6201BGLE
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： DIGITAL SIGNAL PROCESSORS
中文描述： 數(shù)字信號處理器
文件頁數(shù)： 32/73頁
文件大?。?/td> 1093K
代理商： SMJ320C6201BGLE
SM320C6201, SMJ320C6201B
DIGITAL SIGNAL PROCESSORS
SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999
32
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
INPUT AND OUTPUT CLOCKS (CONTINUED)
switching characteristics for CLKOUT2
(see Figure 11)
NO.
PARAMETER
’C6201-150
’C6201B-150
’C6201B-200
UNIT
MIN
MAX
MIN
MAX
1
tc(CKO2)
tw(CKO2H)
tw(CKO2L)
tt(CKO2)
Cycle time, CLKOUT2
2P – 0.7*
2P + 0.7*
2P – 0.7
2P + 0.7
ns
2
Pulse duration, CLKOUT2 high
P – 0.7*
P + 0.7*
P – 0.7
P + 0.7
ns
3
Pulse duration, CLKOUT2 low
P – 0.7*
P + 0.7*
P – 0.7
P + 0.7
ns
4
Transition time, CLKOUT2
0.6*
0.6
ns
P = 1/CPU clock frequency in ns.
*This parameter is not production tested.
CLKOUT2
1
2
3
4
4
Figure 11. CLKOUT2 Timings
SDCLK, SSCLK timing parameters
SDCLK timing parameters are the same as CLKOUT2 parameters.
SSCLK timing parameters are the same as CLKOUT1 or CLKOUT2 parameters, depending on SSCLK
configuration.
switching characteristics for the relation of SSCLK, SDCLK, and CLKOUT2 to CLKOUT1
(see Figure 12)
NO.
PARAMETER
’C6201-150
’C6201B-150
’C6201B-200
UNIT
MIN
MAX
MIN
MAX
1
td(CKO1-SSCLK)
Delay time, CLKOUT1 edge to SSCLK edge
–1.2*
1.6*
(P/2) + 0.2
(P/2) + 4.2
ns
2
td(CKO1-SSCLK1/2)
Delay time, CLKOUT1 edge to SSCLK edge
(1/2 clock rate)
–1.0*
2.4*
(P/2) – 1
(P/2) + 2.4
ns
3
td(CKO1-CKO2)
td(CKO1-SDCLK)
Delay time, CLKOUT1 edge to CLKOUT2 edge
–1.0*
2.4*
(P/2) – 1
(P/2) + 2.4
ns
4
Delay time, CLKOUT1 edge to SDCLK edge
–1.0*
2.4*
(P/2) – 1
(P/2) + 2.4
ns
P = 1/CPU clock frequency in ns.
*This parameter is not production tested.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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