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SMH4046
Preliminary Information
Summit Microelectronics, Inc
2082 1.7 08/23/04
26
Register R04 – Over-Current Configuration.
Bit D[7] and D[5] are unused. Bit D[6] controls if OC causes an IRQ and D[4] controls if OC causes a FAULT. Bits
D[3:0] control the overcurrent Delay.
Register R04
D7
D6
D5
D4
D3
D2
D1
D0
0
-
-
-
-
-
-
-
-
0
-
-
-
-
-
-
-
1
-
-
-
-
-
-
-
-
0
-
-
-
-
-
-
-
-
0
-
-
-
-
-
-
-
1
-
-
-
-
Action
Unused
OC does not cause an IRQ
OC causes an IRQ
Unused
OC does not cause a FAULT
OC causes a FAULT
Minimum Overcurrent Delay = 5.5
μ
s, 1LSB=3
μ
s
Maximum Overcurrent Delay = 50.5
μ
s
-
-
-
-
0
0
0
0
-
-
-
-
1
1
1
1
Register R05 – Overcurrent configuration and fault latch.
Bits D[7:6] control the VDD differential level that causes an OC. Bits D[5:4] control the VCC3 differential level that
causes an OC. Bit D[3] controls the 5V OC detection. Bit D[2] controls the 3V OC detection. Bit D[1] controls the
FAULT output latch and D[0] is unused.
Register R05
D7
D6
D5
D4
D3
D2
D1
D0
Action
0
0
-
-
-
-
-
-
50mV differential between VDD and CARD5V
causes OC
100mV differential between VDD and CARD5V
causes OC
150mV differential between VDD and CARD5V
causes OC
250mV differential between VDD and CARD5V
causes OC
50mV differential between VCC3 and CARD3V
causes OC
100mV differential between VCC3 and CARD3V
causes OC
150mV differential between VCC3 and CARD3V
causes OC
250mV differential between VCC3 and CARD3V
causes OC
OC detection on 5V channel OFF
OC detection on 5V channel ON
OC detection on 3V channel OFF
OC detection on 3V channel ON
Fault output is unlatched
Fault output is latched
Unused
0
1
-
-
-
-
-
-
1
0
-
-
-
-
-
-
1
1
-
-
-
-
-
-
-
-
0
0
-
-
-
-
-
-
0
1
-
-
-
-
-
-
1
0
-
-
-
-
-
-
1
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
1
-
-
-
-
-
-
-
0
1
-
-
-
-
-
-
-
-
-
-
-
-
-
0
0
1
-
CONFIGURATION REGISTERS (CONTINUED)