
SMH4046
PIN DESCRIPTIONS
Preliminary Information
Summit Microelectronics, Inc
2082 1.7 08/23/04
5
Symbol
Pin
Type
Description
SCL
1
I
The I
2
C serial bus clock.
A2
2
I
An external address bit for I
2
C.
HST_RST
3
I
Host reset. This input is the reset signal from the host interface. Asserting this
pin causes a reset sequence to be performed on the card. Programmable
polarity.
Host power-up enable. This input provides the host system with active control
over the sequencing of the power up operation. When de-asserted, the
SMH4046 holds the add-in card in reset and blocks all power to the back-end
logic. When HST_PWR is asserted, the power sequencing begins immediately
and the reset output is driven active after the time tPURST. Programmable
polarity.
Force Shutdown. This programmable active high/low input is used to
immediately turn off all converter enable signals and external FETs.
This input can be used to sense a voltage generated from an external
temperature monitoring device.
Active low Interrupt output. Generated by the SMH4046 on an error condition.
This signal can be used by external logic to interrupt the host.
RESET is a programmable active high/low open drain output that is asserted
by the SMH4046 when a programmed reset condition occurs.
FAULT is a programmable active high/low open drain fault output that is
asserted by the SMH4046 when a programmed fault condition occurs.
Healthy is a programmable active high/low open drain output that is asserted
by the SMH4046 when all programmed healthy conditions are met.
HST_PWR
4
I
FS
5
I
EXT_TEMP
6
I
IRQ#
7
O
RESET (RST)
8
O
FAULT
9
O
HEALTHY
10
O
GND
11
PWR Ground.
PND1#
12
I
Pin detect 1 is an active low CMOS level input. In conjunction with PND2#,
this signal indicates proper card insertion when taken low. This pin must be
connected to ground on the host side of the connector. PND1# and PND2#
should be placed on opposite corners of the connector and will preferably be
staggered shorter than the power connector pins. Board insertion is assumed
when PND1# and PND2# are low.
Pin detect 2 is an active low CMOS level input. In conjunction with PND1#,
this signal indicates proper card insertion when taken low. This pin must be
connected to ground on the host side of the connector. PND1# and PND2#
should be placed on opposite corners of the connector and will preferably be
staggered shorter than the power connector pins. Board insertion is assumed
when PND1# and PND2# are low.
Card voltage valid. This open drain output indicates that the card side voltages
are at or above their respective trip levels. Active high.
PND2#
13
I
CARD_V_VLD
14
O
VMA
15
I
Positive converter sense line for DC/DC converter A
TRIMA
16
O
Output voltage used to control the output of DC/DC converter A.
TRIM_CAPA
17
I
External sample and hold capacitor input used to set the voltage on the
TRIMA pin.