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參數(shù)資料
| 型號： | SMH4044 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | Compact PCI Hot-Swap Controller With IPMI Support |
| 中文描述： | 緊湊型PCI熱插拔控制器支持符合IPMI |
| 文件頁數(shù)： | 15/20頁 |
| 文件大?。?/td> | 503K |
| 代理商： | SMH4044 |
15
2057 1.x 8/16/01
SMH4044
SUMMIT MICROELECTRONICS, Inc.
Preliminary
Table 2. Memory Timing
Figure 6. Memory Timing
2057 Table02
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1
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7
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Note: (1) These values are guaranteed by design.
BUS INTERFACE
GENERAL DESCRIPTION
The I
2
C bus is a two-way, two-line serial communication
between different integrated circuits. The two lines are:
a serial Data line (SDA) and a serial Clock line (SCL). All
Summit Microelectronics parts support a 100kHz clock
rate, and some support the alternative 400kHz clock.
Check Table 2 for the value of f
SCL
. The SDA line must
be connected to a positive supply by a pull-up resistor
located on the bus. Summit parts have Schmitt Trigger
inputs on both lines. See Figure 6 and Table 2 for
waveforms and timing on the bus. One bit of Data is
transferred during each Clock pulse. The Data must
remain stable when the Clock is high.
tF
tR
tLOW
tHIGH
tHD:STA
tSU:STA
tBUF
tDH
tHD:DAT
tSU:DAT
tSU:STO
SCL
SDA In
SDA Out
tAA
2057 Fig06
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| SMH4046 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Hot-Swap, Active DC Output Control (ADOCTM) Power Manager with I2C lnterface |
| SMH4046F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Hot-Swap, Active DC Output Control (ADOCTM) Power Manager with I2C lnterface |
| SMH4046FC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Hot-Swap, Active DC Output Control (ADOCTM) Power Manager with I2C lnterface |
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