參數(shù)資料
型號: SMH4042ASAHM
廠商: Electronic Theatre Controls, Inc.
英文描述: TERM 5"7 TS GRAPH. MONO LOW END VERS.
中文描述: 分布式電源熱插拔控制器的CompactPCI
文件頁數(shù): 11/28頁
文件大小: 1822K
代理商: SMH4042ASAHM
2070 9.1 5/27/03
SMH4042A
SUMMIT MICROELECTRONICS, Inc.
11
BUS INTERFACE
GENERAL DESCRIPTION
The I
2
C bus is a two-way, two-line serial communication
between different integrated circuits. The two lines are:
a serial Data line (SDA) and a serial Clock line (SCL). All
Summit Microelectronics parts support a 100kHz clock
rate, and some support the alternative 400kHz clock.
Check Table 2 for the value of f
SCL
. The SDA line must
be connected to a positive supply by a pull-up resistor
located on the bus. Summit parts have a Schmitt input on
both lines. See Figure 5 and Table 2 for waveforms and
timing on the bus. One bit of Data is transferred during
each Clock pulse. The Data must remain stable when the
Clock is high.
Figure 5. I
2
C Timing Diagram
Table 2. I
2
C AC Operating Characteristics
2037 Table02 2.0
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Note 1 - Guaranteed by Design
tF
tR
tLOW
tHIGH
tHD:SDA
tSU:SDA
tBUF
tDH
tHD:DAT
tSU:DAT
tSU:STO
SCL
SDA In
SDA Out
tAA
2070 Fig05
相關PDF資料
PDF描述
SMH4042ASAHN TERM 5"7 TS GRAPH. MONO STD. VERS.
SMH4042ASAKM TERM.5"7 TS GRAPH. C.STN LOW END VERS.
SMH4042ASAKN TERM.5"7 TS GRAPH. C.TFT STD. VERS.
SMH4042ASALM TERM.7"5 TS GRAPH. C.STN STD. VERS.
SMH4042ASALN TERM.7"5 TS GRAPH. C.TFT STD. VERS.
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