參數(shù)資料
型號(hào)： SMH4042AGBKN
廠商： Electronic Theatre Controls, Inc.
元件分類： 基準(zhǔn)電壓源/電流源
英文描述： Distributed Power Hot-Swap Controller for CompactPCI
中文描述： 分布式電源熱插拔控制器的CompactPCI
文件頁(yè)數(shù)： 13/28頁(yè)
文件大小： 1822K
代理商： SMH4042AGBKN
2070 9.1 5/27/03
SMH4042A
SUMMIT MICROELECTRONICS, Inc.
13
Random Address Read
Random address Read operations allow the Master to
access any memory location in a random fashion. This
operation involves a two-step process. First, the Master
issues a write command which includes the start condi-
tion and the Slave address field (with the R/W bit set to
Write) followed by the address of the word it is to read.
This procedure sets the internal address counter of the
SMH4042A to the desired address. After the word address
Acknowledge is received by the Master, it immediately
reissues a start condition followed by another Slave
address field with the R/W bit set to Read. The SMH4042A
will respond with an Acknowledge and then transmit the
8 data bits stored at the addressed location. At this point
the Master sets SDA high (NACK) and generates a Stop
condition. The SMH4042A discontinues data transmission
and reverts to its standby power mode.
Sequential Read
Sequential Reads can be initiated as either a current
address Read or a random access Read. The first word
is transmitted as with the other byte read modes (current
address byte Read or random address byte Read).
However, the Master now responds with an Acknowl-
edge, indicating that it requires additional data from the
SMH4042A. The SMH4042A continues to output data for
each Acknowledge received. The Master terminates the
sequential Read operation with a NACK and issues a Stop
condition. During a sequential read operation the internal
address counter is automatically incremented with each
Acknowledge signal. For read operations all address bits
are incremented, allowing the entire array to be read using
a single Read command. After a count of the last memory
address the address counter will roll-over and the
memory will continue to output data.
Figure 9. Basic Read
Figure 10. Basic Write
Master
SDA
Slave
S
T
A
R
T
1 0
R
/
W
1 0
A
C
K
x x x R x x x x x x x x
A
C
K
x x
x x
N
A
C
K
S
T
O
P
Optional
2070 Fig09
Master
SDA
Slave
S
T
A
R
T
1 0
R
/
W
1 0
A
C
K
x x x W
x x x x x x x x
x x
x x
A
C
K
A
C
K
S
T
O
P
2070 Fig10
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