參數(shù)資料
型號: SLA24C32-S-3
廠商: SIEMENS A G
元件分類: DRAM
英文描述: 32 Kbit 4096 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus
中文描述: 4K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8
封裝: PLASTIC, DSO-8
文件頁數(shù): 12/26頁
文件大?。?/td> 357K
代理商: SLA24C32-S-3
SLx 24C32
Semiconductor Group
12
Preliminary 1998-07-27
5.2
Page Write
Those bytes of the page that have not been addressed are not included in the
programming.
Figure 8
Page Write Sequence
Address Setting
The page write procedure is the same as the byte write
procedure up to the first data byte. In a page write instruction
however, entry of the EEPROM address bytes AHI/ALO are
followed by a sequence of one to a maximum of 32 data bytes
with the new data to be programmed. These bytes are
transferred to the internal page buffer of the EEPROM.
The first entered data byte will be stored according to the
EEPROM address n given by AHI (A8 to A11) and ALO (A0 to
A7).
The
internal
address
automatically
after
the
entered
acknowledged. The next data byte is then stored at the next
higher EEPROM address. EEPROM addresses within the
same page have common page address bits A5 through A11.
Only the respective five least significant address bits A0
through A4 are incremented, as all data bytes to be
programmed simultaneously have to be within the same page.
Writing over the page border will cause the address counter to
roll over to the first address of the page.
The master stops data entry by applying a STOP condition,
which also starts the internally timed erase/write cycle. In the
first step, all selected bytes are erased to “1”. With the next
internal step, the addressed bytes are written according to the
contents of the page buffer.
Transmission of Data
counter
data
is
byte
incremented
has
been
Programming Cycle
T
O
P
S
Bus Activity
Master
SDA Line
Bus Activity
EEPROM
IED02519
P
R
T
A
T
S
Command
Byte
CSW
EEPROM
Address
ALO
Byte n
Data
Byte n+1
Data
Byte n+31
Data
C
K
A
0
...
C
K
A
C
K
A
C
K
A
C
K
A
EEPROM
Address
AHI
K
C
A
S
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