- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄9577 > SI5324D-C-GMR (Silicon Laboratories Inc)IC CLOCK MULT 2KHZ-150MHZ 36VQFN PDF資料下載
參數(shù)資料
| 型號(hào)： | SI5324D-C-GMR |
| 廠商： | Silicon Laboratories Inc |
| 文件頁(yè)數(shù)： | 1/72頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK MULT 2KHZ-150MHZ 36VQFN |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 系列： | DSPLL® |
| 類型： | 時(shí)鐘/頻率倍增器，抖動(dòng)衰減器，多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)（WAN），SONET/SDH/STM，視頻 |
| 輸入： | 時(shí)鐘 |
| 輸出： | CML，CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 150MHz |
| 電源電壓： | 1.71 V ~ 3.63 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 36-VFQFN 裸露焊盤(pán) |
| 供應(yīng)商設(shè)備封裝： | 36-QFN（6x6） |
| 包裝： | 帶卷 (TR) |
當(dāng)前第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)
Rev. 1.1 1/14
Copyright 2014 by Silicon Laboratories
Si5324
Features
Applications
Description
The Si5324 is a low-bandwidth, jitter-attenuating, precision clock multiplier
for applications requiring sub 1 ps jitter performance with loop bandwidths
between 4 Hz and 525 Hz. The Si5324 accepts two input clocks ranging
from 2 kHz to 710 MHz and generates two output clocks ranging from 2 kHz
to 945 MHz and select frequencies to 1.4 GHz. The two outputs are divided
down separately from a common source. The Si5324 can also use its
external reference as a clock source for frequency synthesis. The device
provides virtually any frequency translation combination across this
operating range. The Si5324 input clock frequency and clock multiplication
ratio are programmable via an I2C or SPI interface. The Si5324 is based on
Silicon Laboratories' 3rd-generation DSPLL technology, which provides
any-frequency synthesis and jitter attenuation in a highly integrated PLL
solution that eliminates the need for external VCXO and filter components.
The DSPLL loop bandwidth is digitally programmable, providing jitter
performance optimization at the application level. The Si5324 is ideal for
providing clock multiplication and jitter attenuation in high performance
timing applications.
Generates any frequency from
2 kHz to 945 MHz and select
frequencies to 1.4 GHz from an
input frequency of 2 kHz to
710 MHz
Ultra-low jitter clock outputs as low
as 290 fs rms (12 kHz–20 MHz),
320 fs rms (50 kHz–80 MHz)
Integrated loop filter with
selectable loop bandwidth
(4– 525 Hz)
Meets ITU-T G.8251 and Telcordia
GR-253-CORE jitter specification
Hitless input clock switching with
phase build-out
Freerun, Digital Hold operation
Configurable signal format per
output (LVPECL, LVDS, CML,
CMOS)
Support for ITU G.709 and custom
FEC ratios (255/238, 255/237,
255/236, 239/237, 66/64, 239/238,
15/14, 253/221, 255/238)
LOL, LOS, FOS alarm outputs
I2C or SPI programmable
On-chip voltage regulator with high
PSNR
Single supply 1.8 ±5%, 2.5 ±10%,
or 3.3 V ±10%
Small size: 6 x 6 mm 36-lead QFN
Pb-free, ROHS-compliant
Broadcast video –3G/HD/SD-SDI,
Genlock
Packet Optical Transport Systems
(P-OTS), MSPP
OTN/OTU-1/2/3/4 Asynchronous
Demapping (Gapped Clock)
SONET OC-48/192/768,
SDH/STM-16/64/256 line cards
1/2/4/8/10G Fibre Channel line
cards
GbE/10/40/100G Synchronous
Ethernet (LAN/WAN)
Data converter clocking
Wireless base stations
Test and measurement
ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/
JITTER ATTENUATOR
Ordering Information:
See page 64.
Pin Assignments
1
2
3
29
30
31
32
33
34
35
36
20
21
22
23
24
25
26
27
10 11 12 13 14 15 16 17
4
5
6
7
8
NC
RST
C2B
INT_C1B
GND
VDD
XA
VDD
RATE0
CK
IN
2+
CK
IN
2–
NC
RATE1
CK
IN
1+
CK
IN
1–
CS_CA
SCL
SDA_SDO
A1
A2_SS
SDI
CKOUT1
–
NC
GN
D
VDD
NC
CKOUT2–
CKOUT2+
CM
ODE
GND
Pad
A0
GND
9
18
19
28
XB
LO
L
GND
CKOUT1+
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VI-BWR-MW-F3 | CONVERTER MOD DC/DC 7.5V 100W |
| VE-BNP-MY-S | CONVERTER MOD DC/DC 13.8V 50W |
| VE-BNN-MY-S | CONVERTER MOD DC/DC 18.5V 50W |
| SI5319C-C-GMR | IC CLOCK MULT/ATTENUATOR 36QFN |
| EL1517BIYEZ | IC LINE DRIVER XDSL DIFF 10HMSOP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SI5324E-C-GM | 制造商:Silicon Laboratories Inc 功能描述:ANYRATE PRECISION CLOCK - Trays |
| Si5324-EVB | 功能描述:時(shí)鐘和定時(shí)器開(kāi)發(fā)工具 Si5324 Evaluation Board RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評(píng)估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
| SI5325 | 制造商:SILABS 制造商全稱:SILABS 功能描述:Pin-Controlled 1_710 MHz Jitter Cleaning Clock |
| Si5325/26-EVB | 功能描述:時(shí)鐘和定時(shí)器開(kāi)發(fā)工具 Si5325/Si5326 EVAL BOARD RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評(píng)估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
| Si5325A-B-GM | 功能描述:鎖相環(huán) - PLL uP-PROGRAMMABE CLK MULT 10 MHZ-1.4 GHZ RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。