參數(shù)資料
型號： SI4955DY-T1-E3
廠商： Vishay Intertechnology,Inc.
英文描述： Asymmetrical Dual P-Channel 30-V/20-V (D-S) MOSFETs
中文描述： 非對稱雙P溝道30-V/20-V（副）的MOSFET
文件頁數(shù)： 2/9頁
文件大小： 137K
代理商： SI4955DY-T1-E3
www.vishay.com
2
Document Number: 72241
S-61006-Rev. C, 12-Jun-06
Vishay Siliconix
Si4955DY
Notes:
a. Pulse test; pulse width
≤
300 μs, duty cycle
≤
2 %.
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
SPECIFICATIONS
T
J
= 25 °C, unless otherwise noted
Parameter
Static
Symbol
Test Conditions
Min
Typ
Max
Unit
Gate Threshold Voltage
V
GS(th)
V
DS
= V
GS
, I
D
= - 250 μA
V
DS
= V
GS
, I
D
= - 250 μA
V
DS
= 0 V, V
GS
= ± 20 V
V
DS
= 0 V, V
GS
= ± 8 V
V
DS
= - 30 V, V
GS
= 0 V
V
DS
= - 20 V, V
GS
= 0 V
V
DS
= - 30 V, V
GS
= 0 V, T
J
= 85 °C
V
DS
= - 20 V, V
GS
= 0 V, T
J
= 85 °C
V
DS
≥
- 5 V, V
GS
= - 10 V
V
DS
≤
- 5 V, V
GS
= - 10 V
V
GS
= - 10 V, I
D
= - 5.0 A
V
GS
= - 4.5 V, I
D
= - 7.0 A
V
GS
= - 4.5 V, I
D
= - 3.7 A
V
GS
= - 2.5 V, I
D
= - 6.2 A
V
GS
= - 1.8 V, I
D
= - 3 A
V
DS
= - 15 V, I
D
= - 5.0 A
V
DS
= - 15 V, I
D
= - 3 A
I
S
= - 1.7 A, V
GS
= 0 V
I
S
= - 1.7 A, V
GS
= 0 V
Ch-1
- 1.0
- 3
V
Ch-2
- 0.4
- 1
Gate-Body Leakage
I
GSS
Ch-1
± 100
nA
Ch-2
± 100
Zero Gate Voltage Drain Current
I
DSS
Ch-1
- 1
μA
Ch-2
- 1
Ch-1
- 5
Ch-2
- 5
On-State Drain Current
a
I
D(on)
Ch-1
- 20
A
Ch-2
- 20
Drain-Source On-State Resistance
a
r
DS(on)
Ch-1
0.044
0.054
Ω
Ch-2
0.022
0.027
Ch-1
0.082
0.100
Ch-2
0.029
0.035
Ch-2
0.039
0.048
Forward Transconductance
a
g
fs
Ch-1
10
S
Ch-2
25
Diode Forward Voltage
a
V
SD
Ch-1
- 0.80
- 1.2
V
Ch-2
- 0.80
- 1.2
Dynamic
b
Total Gate Charge
Q
g
Channel-1
V
DS
= - 15 V, V
GS
= - 10 V, I
D
= - 5.0 A
Channel-2
V
DS
= - 10 V, V
GS
= - 4.5 V, I
D
= - 7 A
Ch-1
Ch-2
Ch-1
Ch-2
Ch-1
Ch-2
Ch-1
Ch-2
Ch-1
Ch-2
Ch-1
Ch-2
Ch-1
Ch-2
Ch-1
12.5
21
2.1
2.6
3.5
6.0
7
20
10
40
30
125
22
85
25
19
25
nC
Gate-Source Charge
Q
gs
Gate-Drain Charge
Q
gd
Turn-On Delay Time
t
d(on)
Channel-1
V
DD
= - 15 V, R
L
= - 15
Ω
I
D
- 1 A, V
GEN
= - 10 V, R
G
= 6
Ω
Channel-2
V
DD
= - 10 V, R
L
= 10
Ω
I
D
- 1 A, V
GEN
= - 4.5 V, R
G
= 6
Ω
15
30
15
60
45
190
35
130
60
ns
Rise Time
t
r
Turn-Off Delay Time
t
d(off)
Fall Time
t
f
Source-Drain Reverse Recovery Time
t
rr
I
F
= - 1.7 A, di/dt = 100 A/μs
I
F
= - 1.7 A, di/dt = 100 A/μs
Ch-2
64
90
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