參數(shù)資料
型號(hào)： SHARP_LH7A404
廠(chǎng)商： Sharp Corporation
英文描述： 32 BIT SYSTEM ON CHIP
中文描述： 32位片上系統(tǒng)
文件頁(yè)數(shù)： 30/51頁(yè)
文件大?。?/td> 387K
代理商： SHARP_LH7A404
LH7A404
32-Bit System-on-Chip
30
Advance Data Sheet
DC-to-DC Converter
The features of the DC-DC Converter interface are:
Dual drive PWM outputs with independent closed
loop feedback
Software programmable configuration of one of 8
output frequencies (each being a fixed division of the
input clock).
Software programmable configuration of duty cycle
from 0 to 15/16, in intervals of 1/16.
Hardware-configured output polarity (for positive or
negative voltage generation) during power-on reset
via the polarity select inputs
Dynamically switched PWM outputs to one of a pair
of preprogrammed frequency/duty cycle combina-
tions via external pins.
Watchdog Timer (WDT)
The Watchdog Timer provides hardware protection
against malfunctions. It is a programmable timer that is
reset by software at regular intervals. Failure to reset
the timer will cause an FIQ interrupt. Failure to service
the FIQ interrupt generates a system reset. Features of
the WDT:
Timing derived from the system clock
16 programmable time-out periods: 2
16
through 2
31
clock cycles
Generates a system reset (resets LH7A404) or a
FIQ interrupt whenever a time-out period is reached
Software enable, lockout, and counter-reset mecha-
nisms add security against inadvertent writes
Protection mechanism guards against interrupt-ser-
vice-failure:
– The first WDT time-out triggers FIQ and asserts
nWDFIQ status flag
– If FIQ service routine fails to clear nWDFIQ, then
the next WDT time-out triggers a system reset.
General Purpose I/O (GPIO)
The GPIO has eight ports, each with a data register
and a data direction register. It also has added regis-
ters including Keyboard Scan, PINMUX, GPIO Inter-
rupt Enable, INTYPE1/2, GPIOFEOI and PGHCON.
The data direction register determines whether a
port is configured as an input or an output while the
data register is used to read the value of the GPIO pins.
The GPIO Interrupt Enable, INTYPE1/2, and the
GPIOFEOI registers control edge-triggered Interrupts
on Port F. The PINMUX register controls which signals
are from Port D and Port E when they are set as out-
puts, while the PGHCON controls the operations of
Port G and Port H.
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