參數(shù)資料
型號(hào)： SHARP_LH7A404
廠商： Sharp Corporation
英文描述： 32 BIT SYSTEM ON CHIP
中文描述： 32位片上系統(tǒng)
文件頁(yè)數(shù)： 27/51頁(yè)
文件大小： 387K
代理商： SHARP_LH7A404
32-Bit System-on-Chip
LH7A404
Advance Data Sheet
27
USB Host Controller
The features of the USB Host Controller are:
Open Host Controller Interface Specification (Open-
HCI) Rev. 1.0 compatible
Universal Serial Bus Specification Rev. 1.1 compatible
Support for both Low Speed and High Speed USB
devices
Root Hub has two Downstream Ports
DMA functionality.
Color LCD Controller
The LH7A404’s LCD Controller is programmable to
support up to 1,024 × 768, 16-bit color LCD panels. It
interfaces directly to STN, color STN, TFT, and HR-TFT
panels. Unlike other LCD controllers, the LH7A404’s
LCD Controller incorporates the timing conversion logic
from TFT to HR-TFT, allowing a direct interface to HR-
TFT and minimizing external chip count.
The Color LCD Controller features support for:
Up to 1,024 × 768 Resolution
16-bit Video Bus
STN, Color STN, HR-TFT, TFT panels
Single and Dual Scan STN panels
Up to 15 Gray Shades
Up to 64 k-Colors
Advanced Audio Codec (AAC)
The Advanced Audio Codec controller (AC97)
includes a 5-pin serial interface to an external audio
codec. The AAC link is a bi-directional, fixed rate, serial
Pulse Code Modulation (PCM) digital stream, dividing
each audio frame into 12 outgoing and 12 incoming data
streams (slots), each with 20-bit sample resolution.
The AAC controller contains logic that controls the
AAC link to the audio codec and an interface to the
AMBA APB.
Its main features include:
Serial-to-parallel conversion for data received from
the external codec
Parallel-to-serial conversion for data transmitted to
the external codec
Reception/transmission of control and status infor-
mation via the AMBA APB interface
Support for up to 4 different codec sampling rates at
a time with its 4 transmit and 4 receive channels. The
transmit and receive paths are buffered with internal
FIFO memories, allowing data to be stored indepen-
dently in both transmit and receive modes. The out-
going data for the FIFOs can be written via either the
APB interface or with DMA channels 1-3.
Audio Codec Interface (ACI)
The ACI provides:
A digital serial interface to an off-chip 8-bit codec
All the necessary clocks and timing pulses to per-
form serialization or de-serialization of the data
stream to or from the codec device.
The interface supports full duplex operation and the
transmit and receive paths are buffered with internal
FIFO memories allowing up to 16 bytes to be stored
independently in both transmit and receive modes.
The ACI includes a programmable frequency divider
that generates a common transmit and receive bit clock
output from the on-chip ACI clock input (ACICLK).
Transmit data values are output synchronous with the
rising edge of the bit clock output. Receive data values
are sampled on the falling edge of the bit clock output.
The start of a data frame is indicated by a synchroniza-
tion output signal that is coincident with the bit clock.
Pulse Width Modulator (PWM)
The Pulse Width Modulator features:
Configurable dual output
Separate input clocks for each PWM output
16-bit resolution
Programmable synchronous mode support
– Allows external input to start PWM
Programmable pulse width (duty cycle), interval (fre-
quency), and polarity
– Static programming: when the PWM is stopped
– Dynamic programming: when the PWM is running
– Updates duty cycle, frequency, and polarity at
end of a PWM cycle
The PWM is a configurable dual-output, dual-clock-
input AMBA slave module, and connects to the APB.
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