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參數(shù)資料
| 型號： | SHARP_LH7A404 |
| 廠商： | Sharp Corporation |
| 英文描述： | 32 BIT SYSTEM ON CHIP |
| 中文描述： | 32位片上系統(tǒng) |
| 文件頁數(shù)： | 25/51頁 |
| 文件大?。?/td> | 387K |
| 代理商： | SHARP_LH7A404 |
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32-Bit System-on-Chip
LH7A404
Advance Data Sheet
25
The SD/MMC bus lines can be divided into three
groups:
Power supply: VSS1, VSS2 and VDD
Data transfer: MMCCMD, MMCDAT0, MMCDAT1,
MMCDAT2, MMCDAT3 (for MMC, do not use
MMCDAT1, MMCDAT2, MMCDAT3)
Clock: MMCCLK
MMC bus lines can be divided into three groups:
Power supply: VDD and VSS
Data Transfer: MMCCMD, MMCDATA
Clock: MMCLK.
MMC ADAPTER
The MMC Adapter implements MMC specific func-
tions, serves as the bus master for the MMC Bus and
implements the standard interface to the MMC Cards
(card initialization, CRC generation and validation,
command/response transactions, etc.).
Smart Card Interface (SCI)
The SCI (ISO7816) connects to an external Smart
Card reader. The SCI can autonomously control data
transfer to and from the smart card. Transmit and
receive data FIFOs are provided to reduce the required
interaction between the CPU core and the peripheral.
SCI FEATURES
Supports asynchronous T0 and T1 transmission pro-
tocols
Supports clock rate conversion factor F = 372, with
bit rate adjustment factors D = 1, 2, or 4 supported
Eight-character-deep buffered Tx and Rx paths
Direct interrupts for Tx and Rx FIFO level monitoring
Interrupt status register
Hardware-initiated card deactivation sequence on
detection of card removal
Software-initiated card deactivation sequence on
transaction complete
Limited support for synchronous smart cards via reg-
istered input/output.
PROGRAMMABLE PARAMETERS
Smart card clock frequency
Communication baud rate
Protocol convention
Card activation/deactivation time
Check for maximum time for first character of
Answer to Reset (ATR) reception
Check for maximum duration of ATR character
stream
Check for maximum time of receipt of first character
of data stream
Check for maximum time allowed between characters
Character guard time
Block guard time
Transmit/receive character retry.
Direct Memory Access Controller (DMA)
The DMA Controller can be used to interface
streams from 20 internal peripherals to the system
memory using 10 fully-independent programmable
channels which consist of five M2P (transmit) channels
and five P2M (receive) channels.
The following peripherals may be allocated to the 10
channels:
USB Device
USB Host
SD/MMC
AAC
UART1
UART2
UART3
Each of the above peripherals contain one Tx and
one Rx channel, except the AAC, which contains three
Tx and Rx channels. These peripherals also have their
own bi-directional DMA bus, capable of simultaneously
transferring data in both directions. All memory trans-
fers take place via the main system AHB bus.
The DMA Controller can also be used to interface
streams from memory-to-memory (M2M) or memory-
to-external peripheral (M2P) using two dedicated M2M
channels. External handshake signals are available to
suport memory-to-/from-external peripheral (M2P/
P2M) transfers. A software trigger is available for M2M
transfers only.
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