參數(shù)資料
型號(hào)： SHARP_LH7A404
廠商： Sharp Corporation
英文描述： 32 BIT SYSTEM ON CHIP
中文描述： 32位片上系統(tǒng)
文件頁(yè)數(shù)： 19/51頁(yè)
文件大小： 387K
代理商： SHARP_LH7A404
32-Bit System-on-Chip
LH7A404
Advance Data Sheet
19
SYSTEM DESCRIPTIONS
ARM922T Processor
The LH7A404 microcontroller features the ARM922T
cached core with an Advanced High-performance Bus
(AHB) interface. The processor is a member of the
ARM9T family of processors. For more information, see
the ARM document, ‘ARM922T Technical Reference
Manual’, available on ARM’s website at www.arm.com.
Clock and State Controller
The clocking scheme in the LH7A404 is based
around two primary oscillator inputs. These are the
14.7456 MHz input crystal and the 32.768 kHz real time
clock oscillator; see Figure 3. The 14.7456 MHz oscil-
lator supplies the main system clock domains for the
LH7A404. The 32.768 kHz oscillator controls the
power-down operations and real time clock peripheral.
The clock and state controller provides the clock gating
and frequency division necessary, and then supplies
the clocks to the processor and rest of the system. The
amount of clock gating that actually takes place
depends on the power saving mode selected.
The 32.768 kHz clock provides the source for the
Real Time Clock tree and power-down logic. This clock
is used for the power state control and is the only clock
in the LH7A404 that runs continuously. The 32.768 kHz
clock is divided down to 1 Hz for the Real Time Clock
counter using a ripple divider to save power.
The 14.7456 MHz source is used to generate the
main system clocks for the LH7A404. It is the source
for PLL1 and PLL2, the primary clock for the peripher-
als, and the source clock to the programmable clock
(PGM) divider.
PLL1 provides the main clock tree for the chip. It gen-
erates the following clocks: FCLK, HCLK, and PCLK.
FCLK is the clock that drives the ARM922T core.
HCLK is the main bus (AHB) clock, as such it clocks
all memory interfaces, bus arbitrators and the AHB
peripherals. HCLK is generated by dividing FCLK by 1,
2, 3, or 4. HCLK can be gated by the system to enable
low power operation.
PCLK is the peripheral bus (APB) clock. It is gener-
ated by dividing HCLK by either 2, 4, or 8.
PLL2 generates a fixed 48 MHz clock signal for the
USB peripheral.
Figure 2. Application Diagram
CODEC
BATTERY
DC to DC
VOLTAGE
GENERATION
CIRCUITRY
MULTIMEDIA
CARD
TOUCH
SCREEN
CONTR.
MMC/SD
SCI
PCMCIA
COMPACT
FLASH
USB
HOST
DEVICE
HOST
SDRAM
SRAM
ROM
FLASH
DMA
AC97
STN/TFT/
HR-TFT
IR
GPIO
SSP
UART
LH7A404
PC
CARD
LH7A404-2
1
2
3
4
5
6
7
8
9
*
0
#
BMI
SMART
CARD
相關(guān)PDF資料
PDF描述
SHD501290 HERMETIC ULTRA LOW DROPOUT LINEAR REGULATOR
SHD526030 POSITIVE ADJUSTABLE 1.5 AMP REGULATOR
SHD526150 LINEAR VOLTAGE REGULATOR THREE TERMINAL-POSITIVE-ADJUSTABLE 3.0 Amp, Low Dropout Voltage TO-257 Hermetic Package
SHD674122 HERMETIC SILICON CARBIDE RECTIFIER
SHD674122B HERMETIC SILICON CARBIDE RECTIFIER
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SHAUN 制造商:Nwazet 功能描述:Raspberry Pi "Shaun" Case
SH-AX1000-CQ352RTFG896-A 制造商:Microsemi Corporation 功能描述:SH-AX1000-CQ352RTFG896-A - Bulk
SH-AX2000-CQ352RTFG896-A 制造商:Microsemi Corporation 功能描述:SH-AX2000-CQ352RTFG896-A - Bulk
SH-AX250-CQ352RTFG484S-A 制造商:Microsemi Corporation 功能描述:SH-AX250-CQ352RTFG484S-A - Bulk
SHB 制造商:PREMO 制造商全稱:PREMO CORPORATION S.L 功能描述:SMD Power Inductors Shielded
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*