
Rev. 6.0, 07/02, page xlv of I
Figure 22.49
DRAM Bus Cycle: DRAM CAS-Before-RAS Refresh
(TRAS[2:0] = 000, TRC[2:0] = 001) ............................................................... 912
DRAM Bus Cycle: DRAM CAS-Before-RAS Refresh
(TRAS[2:0] = 001, TRC[2:0] = 001) ............................................................... 913
DRAM Bus Cycle: DRAM Self-Refresh (TRC[2:0] = 001)............................ 914
PCMCIA Memory Bus Cycle
(1) TED[2:0] = 000, TEH[2:0] = 000, No Wait
(2) TED[2:0] = 001, TEH[2:0] = 001, One Internal Wait +
One External Wait............................................................................................ 915
PCMCIA I/O Bus Cycle
(1) TED[2:0] = 000, TEH[2:0] = 000, No Wait
(2) TED[2:0] = 001, TEH[2:0] = 001, One Internal Wait +
One External Wait............................................................................................ 916
PCMCIA I/O Bus Cycle (TED[2:0] = 001, TEH[2:0] = 001,
One Internal Wait, Bus Sizing) ........................................................................ 917
MPX Basic Bus Cycle: Read
(1) 1st Data (One Internal Wait)
(2) 1st Data (One Internal Wait + One External Wait)..................................... 918
MPX Basic Bus Cycle: Write
(1) 1st Data (No Wait)
(2) 1st Data (One Internal Wait)
(3) 1st Data (One Internal Wait + One External Wait)..................................... 919
MPX Bus Cycle: Burst Read
(1) 1st Data (One Internal Wait), 2nd to 8th Data (One Internal Wait)
(2) 1st Data (One Internal Wait), 2nd to 4th Data (One Internal Wait +
One External Wait)........................................................................................... 920
MPX Bus Cycle: Burst Write
(1) No Internal Wait
(2) 1st Data (One Internal Wait), 2nd to 4th Data (No Internal Wait +
External Wait Control)..................................................................................... 921
Memory Byte Control SRAM Bus Cycles
(1) Basic Read Cycle (No Wait)
(2) Basic Read Cycle (One Internal Wait)
(3) Basic Read Cycle (One Internal Wait + One External Wait)...................... 922
Memory Byte Control SRAM Bus Cycle: Basic Read Cycle
(No Wait, Address Setup/Hold Time Insertion, AnS[0] = 1, AnH[1:0] =01) .. 923
TCLK Input Timing......................................................................................... 930
RTC Oscillation Settling Time at Power-On.................................................... 930
SCK Input Clock Timing ................................................................................. 930
SCI I/O Synchronous Mode Clock Timing...................................................... 931
I/O Port Input/Output Timing........................................................................... 931
Figure 22.66(a)
'5(4
/DRAK Timing...................................................................................... 931
Figure 22.66(b)
'%5(4
/
75
Input Timing and
%$9/
Output Timing..................................... 932
Figure 22.50
Figure 22.51
Figure 22.52
Figure 22.53
Figure 22.54
Figure 22.55
Figure 22.56
Figure 22.57
Figure 22.58
Figure 22.59
Figure 22.60
Figure 22.61
Figure 22.62
Figure 22.63
Figure 22.64
Figure 22.65