
Rev. 4.00, 03/04, page xlv of xlvi
Table 18.4
Table 18.5
Table 18.6
Table 18.7
Table 18.8
Table 18.9
Table 18.10
Read/Write Operation of the Port D Data Register (PDDR)................................484
Read/Write Operation of the Port E Data Register (PEDR) .................................486
Read/Write Operation of the Port F Data Register (PFDR)..................................487
Read/Write Operation of the Port G Data Register (PGDR).................................489
Read/Write Operation of the Port H Data Register (PHDR).................................491
Read/Write Operation of the Port J Data Register (PJDR)...................................492
Read/Write Operation of the SC Port Data Register (SCPDR).............................494
Section 19 A/D Converter (ADC)
Table 19.1 A/D Converter Pins...................................................................................................497
Table 19.2
Analog Input Channels and A/D Data Registers...................................................498
Table 19.3
A/D Conversion Time (Single Mode)...................................................................509
Table 19.4
Analog Input Pin Ratings......................................................................................512
Table 19.5
Relationship between Access Size and Read Data................................................512
Section 20 D/A Converter (DAC)
Table 20.1
D/A Converter Pins...............................................................................................514
Section 21 User Debugging Interface (H-UDI)
Table 21.1
Pin Configuraiton..................................................................................................518
Table 21.2
This LSI's Pins and Boundary Scan Register Bits.................................................520
Table 21.3
Reset Configuration..............................................................................................526
Section 22 Power-Down Modes
Table 22.1
Power-Down Modes .............................................................................................531
Table 22.2
Pin Configuration..................................................................................................532
Table 22.3
Register States in Software Standby Mode...........................................................536
Section 24 Electrical Characteristics
Table 24.1
Absolute Maximum Ratings .................................................................................569
Table 24.2
DC Characteristics (Ta = –20 to 75°C).................................................................571
Table 24.3
Permitted Output Current Values (VccQ = 3.3 ± 0.3 V, Vcc = 1.9 ± 0.15 V,
AVcc = 3.3 ± 0.3 V, Ta = –20 to 75°C)................................................................573
Table 24.4
Operating Frequency Range..................................................................................574
Table 24.5
Clock Timing........................................................................................................574
Table 24.6
Control Signal Timing ..........................................................................................580
Table 24.7
Bus Timing (Clock Modes 0/1/2/7).....................................................................583
Table 24.8
Peripheral Module Signal Timing.........................................................................615
Table 24.9
H-UDI, AUD Related Pin Timing ........................................................................618
Table 24.10
A/D Converter Timing..........................................................................................620
Table 24.11
A/D Converter Characteristics (VccQ = 3.3 ± 0.3 V, Vcc = 1.9 ± 0.15 V,
AVcc = 3.3 ± 0.3 V, Ta = –20 to 75°C)................................................................624
Table 24.12
D/A Converter Characteristics (VccQ = 3.3 ± 0.3 V, Vcc = 1.9 ± 0.15 V,
AVcc = 3.3 ± 0.3 V, Ta = –20 to 75°C)................................................................624