
viii
12.3.5 Timing of Watchdog Timer Overflow Flag (WOVF) Setting.............................. 329
Usage Notes ....................................................................................................................... 330
12.4.1 Contention between WTCNT Write and Increment............................................. 330
12.4.2 Changing CKS2 to CKS0 Bit Values................................................................... 330
12.4.3 Switching between Watchdog Timer and Interval Timer Mode.......................... 330
12.4.4 System Reset with
WDTOVF
.............................................................................. 331
12.4.5 Internal Reset in Watchdog Timer Mode.............................................................. 331
12.4
Section 13 Serial Communication Interface
................................................................. 333
13.1
Overview............................................................................................................................ 333
13.1.1 Features................................................................................................................. 333
13.1.2 Block Diagram...................................................................................................... 334
13.1.3 Pin Configuration.................................................................................................. 334
13.1.4 Register Configuration.......................................................................................... 335
13.2
Register Descriptions......................................................................................................... 335
13.2.1 Receive Shift Register (RSR)............................................................................... 335
13.2.2 Receive Data Register (RDR)............................................................................... 335
13.2.3 Transmit Shift Register (TSR).............................................................................. 336
13.2.4 Transmit Data Register (TDR).............................................................................. 336
13.2.5 Serial Mode Register (SMR)................................................................................ 336
13.2.6 Serial Control Register (SCR).............................................................................. 339
13.2.7 Serial Status Register (SSR)................................................................................. 342
13.2.8 Bit Rate Register (BRR)....................................................................................... 346
13.3
Operation............................................................................................................................ 352
13.3.1 Overview............................................................................................................... 352
13.3.2 Operation in Asynchronous Mode........................................................................ 354
13.3.3 Multiprocessor Communication............................................................................ 364
13.3.4 Clocked Synchronous Operation.......................................................................... 371
13.4
SCI Interrupt Sources and the DMAC............................................................................... 381
13.5
Usage Notes ....................................................................................................................... 381
Section 14 Power-Down Modes
...................................................................................... 385
14.1
Overview............................................................................................................................ 385
14.1.1 Power-Down Modes............................................................................................. 385
14.1.2 Register................................................................................................................. 386
14.2
Description of Register...................................................................................................... 387
14.2.1 Standby Control Register (SBYCR)..................................................................... 387
14.3
Sleep Mode........................................................................................................................ 389
14.3.1 Transition to Sleep Mode...................................................................................... 389
14.3.2 Canceling Sleep Mode.......................................................................................... 389
14.4
Standby Mode.................................................................................................................... 389
14.4.1 Transition to Standby Mode.................................................................................. 389
14.4.2 Canceling Standby Mode...................................................................................... 390