
Rev. 2.0, 09/02, page 723 of 732
Item
Page
Revisions (See Manual for Details)
24.3.2 Software
Standby Mode
630
Description amended.
Clearing by the IRQ interrupt input
When the falling edge or rising edge of the
IRQ
pin
(selected by the IRQ7S to IRQ0S bits in ICR1 of the
interrupt controller (INTC) and the IRQ7ES[1:0] to
IRQ0ES[1:0] bits in ICR2) is detected, clock oscillation is
started
*
. This clock pulse is supplied only to the
watchdog timer (WDT). The IRQ interrupt priority level
should be higher than the interrupt mask level set in the
status register (SR) of the CPU before the transition to
software standby mode.
Added.
24.4.5 DMAC, DTC, or
AUD Operation in
Sleep Mode
632
Item, Min, Typ, and Max values, and Measurement
conditions amended.
Item
Symbol
Min
Typ
Max
Unit
Measurement
Conditions
RES
,
MRES
,
NMI, FWP, MD3
to MD0, DBGMD
V
IH
V
CC
-0.5
V
CC
+0.3
V
EXTAL
V
CC
-0.5
V
CC
+0.3
V
A/D port
2.2
AV
CC
+ 0.3
V
Input high-level
voltage (except
Schmitt trigger
input voltage)
Other input pins
2.2
V
CC
+0.3
V
V
T+
V
CC
-0.5
V
Schmitt trigger
input voltage
IRQ7
to
IRQ0
,
POE3
to
POE0
,
TCLKA to
V
T-
0.5
V
Output high-
level voltage
All output pins
V
OH
V
CC
-0.5
V
I
OH
= -200
μ
A
Output low-
level voltage
All output pins
V
OL
0.4
V
IOL = 1.6mA
RES
C
in
20
pF
Input
capacitance
NMI
20
pF
Vin = 0 V
f = 1 MHz
Ta = 25
°
C
Clock
1:1
Icc
150
210
mA
f = 40 MHz
Current
consumption
*
2
Normal
operation
Clock
1:1/2
160
220
mA
f = 50 MHz
Clock
1:1
110
170
mA
f = 40 MHz
Sleep
Clock
1:1/2
120
180
mA
f = 50 MHz
Standby
3
50
μ
A
T
a
≤
50
°
C
500
μ
A
50
°
C < T
a
Clock
1:1
150
210
mA
V
CC
= 3.3V
f = 40 MHz
Flash
program-
ming
Clock
1:1/2
160
220
mA
V
CC
= 3.3V
f = 50MHz
Table 26.2 DC
Characteristics
666,
667