
Rev. 2.0, 09/02, page 672 of 732
26.3.3
Control Signal Timing
Table 26.5 shows control signal timing.
Table 26.5 Control Signal Timing
Conditions: V
CC
= PLLV
CC
=3.3 V ± 0.3 V, AV
CC
= 3.3 V ± 0.3 V, AV
CC
= V
CC
± 0.3 V,
AV
ref
= 3.0 V to AV
CC
, V
SS
= PLLV
SS
= AV
SS
= 0 V, T
a
= –20
°
C to +75
°
C
(regular specifications), T
a
= –40
°
C to +85
°
C (wide-range specifications),
When programming or erasing flash memory, T
a
= –20
°
C to +75
°
C.
Item
RES
rise time, fall time
RES
pulse width
RES
setup time
MRES
pulse width
MRES
setup time
Symbol
Min
Max
Unit
Figure
t
RESr
, t
RESf
t
RESW
t
RESS
t
MRESW
t
MRESS
t
MDS
t
NMIr
, t
NMIIf
t
NMIS
t
NMIH
t
IRQES
t
IRQLS
t
IRQEH
t
IRQOD
t
BRQS
t
BACKD1
t
BACKD2
t
BZD
25
200
200
100
35
ns
Figure 26.5
t
cyc
ns
35
20
t
cyc
ns
35
MD3 to MD0 setup time
20
35
t
cyc
ns
NMI rise time, fall time
Figure 26.6
NMI setup time
ns
NMI hold time
IRQ7
to
IRQ0
setup time
*
(edge detection)
IRQ7
to
IRQ0
setup time
*
(level detection)
IRQ7
to
IRQ0
hold time
IRQOUT
output delay time
35
ns
19
ns
19
ns
19
19
ns
ns
Figure 26.7
Bus request setup time
ns
Figure 26.8
Bus acknowledge delay time 1
ns
Bus acknowledge delay time 2
35
ns
Bus three-state delay time
35
ns
[Operating Precautions]
Note: * The
RES
,
MRES,
NMI and
IRQ7
to
IRQ0
signals are asynchronous inputs, but when the
setup times shown here are observed, the signals are considered to have been changed at
clock rise (
RES
,
MRES
) or fall (NMI and
IRQ7
to
IRQ0
). If the setup times are not
observed, the recognition of these signals may be delayed until the next clock rise or fall.