
Rev. 2.0, 09/02, page 53 of 732
Section 5 Exception Processing
5.1
Overview
5.1.1
Types of Exception Processing and Priority
Exception processing is started by four sources: resets, address errors, interrupts and instructions
and have the priority, as shown in table 5.1. When several exception processing sources occur at
once, they are processed according to the priority.
Table 5.1 Types of Exception Processing and Priority Order
Exception Source
Priority
Reset
Power-on reset
High
Manual reset
CPU address error or AUD address error
*
1
Address
error
DMAC/DTC address error
Interrupt
NMI
User break
H-UDI
IRQ
On-chip
peripheral
modules:
Direct memory access controller (DMAC)
Multifunction timer unit (MTU)
Serial communication interface 0 and 1(SCI0 and SCI1)
A/D converter 0 and 1 (A/D0, A/D1)
Data transfer controller (DTC)
Compare match timer 0 and 1 (CMT0, CMT1)
Watchdog timer (WDT)
Input/output port (I/O) (MTU)
Serial communication interface 2 and 3 (SCI2 and SCI3)
IIC bus interface (IIC)
Instructions Trap instruction (TRAPA instruction)
General illegal instructions (undefined code)
Illegal slot instructions (undefined code placed directly after a delay
branch instruction
*
Notes:
1. Only in the F-ZTAT version.
2. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, and
BRAF.
3. Instructions that rewrite the PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA,
BF/S, BT/S, BSRF, and BRAF.
2
or instructions that rewrite the PC
*
3
)
Low