
Rev. 2.0, 09/02, page 642 of 732
Register name
abbreviation
NO. of
bits
Address
Module
Access size
NO. of Access
states
Bus control register 1
BCR1
16
H'FFFF8620
BSC
8, 16, 32
Bus control register 2
BCR2
16
H'FFFF8622
8, 16
Wait control register 1
WCR1
16
H'FFFF8624
8, 16, 32
Wait control register 2
WCR2
16
H'FFFF8626
8, 16
φ
reference
B:3
W:3
L:6
RAM emulation register
RAMER
16
H'FFFF8628
FLASH
(Only in F-ZTAT
version)
8, 16
φ
reference
B:3
W:3
H'FFFF862A to
H'FFFF86AF
DMA operation register
DMAOR
16
H'FFFF86B0
8, 16
φ
reference
H'FFFF86B2 to
H'FFFF86BF
DMAC
(for all channels)
W:3
L:6
DMA source address register_0
SAR_0
32
H'FFFF86C0
DMAC
8, 16, 32
DMA destination address register_0
DAR_0
32
H'FFFF86C4
(Channel 0)
8, 16, 32
DMA transfer count register_0
DMATCR_0
32
H'FFFF86C8
8, 16, 32
DMA channel control register_0
CHCR_0
32
H'FFFF86CC
8, 16, 32
DMA source address register_1
SAR_1
32
H'FFFF86D0
DMAC
8, 16, 32
DMA destination address register_1
DAR_1
32
H'FFFF86D4
(Channel 1)
8, 16, 32
DMA transfer count register_1
DMATCR_1
32
H'FFFF86D8
8, 16, 32
DMA channel control register_1
CHCR_1
32
H'FFFF86DC
8, 16, 32
DMA source address register_2
SAR_2
32
H'FFFF86E0
DMAC
8, 16, 32
DMA destination address register_2
DAR_2
32
H'FFFF86E4
(Channel 2)
8, 16, 32
DMA transfer count register_2
DMATCR_2
32
H'FFFF86E8
8, 16, 32
DMA channel control register_2
CHCR_2
32
H'FFFF86EC
8, 16, 32
DMA source address register_3
SAR_3
32
H'FFFF86F0
DMAC
8, 16, 32
DMA destination address register_3
DAR_3
32
H'FFFF86F4
(Channel 3)
8, 16, 32
DMA transfer count register_3
DMATCR_3
32
H'FFFF86F8
8, 16, 32
DMA channel control register_3
CHCR_3
32
H'FFFF86FC
8, 16, 32