
Rev. 2.0, 09/02, page 16 of 732
Bit
Bit Name
Initial Value
R/W
Description
7
6
5
4
I3
I2
I1
I0
1
1
1
1
R/W
R/W
R/W
R/W
Interrupt mask bits.
3
2
—
—
0
0
R/W
R/W
Reserved bits. This bit is always read as 0.
The write value should always be 0.
1
S
Undefined
R/W
S bit
Used by the MAC instruction.
0
T
Undefined
R/W
T bit
The MOVT, CMP/cond, TAS, TST, BT (BT/S), BF
(BF/S), SETT, and CLRT instructions use the T bit to
indicate true (1) or false (0).
The ADDV, ADDC, SUBV, SUBC, DIV0U, DIV0S,
DIV1, NEGC, SHAR, SHAL, SHLR, SHLL, ROTR,
ROTL, ROTCR, and ROTCL instructions also use the
T bit to indicate carry/borrow or overflow/underflow.
Global Base Register (GBR):
Indicates the base address of the indirect GBR addressing mode.
The indirect GBR addressing mode is used in data transfer for on-chip peripheral modules register
areas and in logic operations.
Vector Base Register (VBR):
Indicates the base address of the exception processing vector area.
2.2.3
System Registers
System registers consist of four 32-bit registers: high and low multiply and accumulate registers
(MACH and MACL), the procedure register (PR), and the program counter (PC).
Multiply-and-Accumulate Registers (MAC):
Registers to store the results of multiply-and-
accumulate operations.
Procedure Register (PR):
Registers to store the return address from a subroutine procedure.
Program Counter (PC):
Registers to indicate the sum of current instruction addresses and four,
that is, the address of the second instruction after the current instruction.