
Rev. 2.0, 09/02, page 483 of 732
16.2.2
Compare Match Timer Control/Status Register 0 and 1(CMCSR0, 1)
The compare match timer control/status register (CMCSR) is a 16-bit register that indicates the
occurrence of compare matches, sets the enable/disable status of interrupts, and establishes the
clock used for incrementation. It is initialized to H'0000 by a power-on reset and in the standby
modes.
Bit
Bit Name Initial Value
R/W
Description
15 to 8
All 0
R
Reserved
These bits always read 0. The write value should
always be 0.
7
CMF
0
R/(W)
*
Compare Match Flag
This flag indicates whether or not the CMCNT and
CMCOR values have matched.
0: CMCNT and CMCOR values have not matched
[Clearing condition]
Write 0 to CMF after reading 1 from it
1: CMCNT and CMCOR values have matched
6
CMIE
0
R/W
Compare Match Interrupt Enable
This bit selects whether to enable or disable a
compare match interrupt (CMI) when the CMCNT and
CMCOR values have matched (CMF = 1).
0: Compare match interrupt (CMI) disabled
1: Compare match interrupt (CMI) enabled
5 to 2
All 0
R
Reserved
These bits always read 0. The write value should
always be 0.
1
0
CKS1
CKS0
0
0
R/W
R/W
These bits select the clock input to CMCNT from
among the four internal clocks obtained by dividing
the peripheral clock (P
φ
). When the STR bit of
CMSTR is set to 1, CMCNT begins incrementing with
the clock selected by CKS1 and CKS0.
00: P
φ
/8
01: P
φ
/32
10: P
φ
/128
11: P
φ
/512
Note:
*
Only 0 can be written, for flag clearing.