
Rev. 2.0, 09/02, page 455 of 732
Table 14.10 Tolerance of the SCL Rise Time (t
Sr
)
Time [ns]
IICX
t
pcyc
I
specification
(max)
2
C bus
P
φ
=
10MHz
P
φ
=
16MHz
P
φ
=
20MHz
P
φ
=
25MHz
P
φ
=
33MHz
P
φ
=
40MHz
Standard
mode
1000
750
468
375
300
227
188
0
7.5
t
pcyc
High-
speed
mode
300
←
←
←
←
227
188
Standard
mode
1000
←
←
875
700
530
438
1
17.5
t
pcyc
High-
speed
mode
300
←
←
←
←
←
←
6. The rise and fall times of SCL and SDA are respectively prescribed as being 1000 ns or less
and 300 ns or less by the I
bus interface of this LSI are described by t
SCLD
and t
pcyc
as shown in table 14.9. However, due to
the effect of the rise and fall times, the I
maximum transfer rate. Table 14.11 shows the results of calculating the output timing for each
available operating frequency, by considering the worst-case rise and fall times. t
BUFO
does not
satisfy the specifications of the I
this problem, either (a) ensure that your program provides the required interval (approximately
1
μ
s) between issuing of the stop condition and of the next start condition or (b) select a slave
device with an input timing that permits use with this output timing for connection to the I
bus.
2
C bus specification. The output timing of SCL and SDA for the I
2
C
2
C bus interface specifications are not satisfied at the
2
C bus interface specifications. As a countermeasure against
2
C
For t
SCLLO
in the high-speed mode and t
STASO
in the standard mode, the I
is not satisfied when the worst case for t
Sr
/t
Sf
is assumed. Take one of the following steps:
2
C bus interface specification
a. Adjust the rise and fall times by changing the pull-up resistors and load capacitance.
b. Reduce the transfer rate until the specification is satisfied.
c.
For connection to the I
with this output timing.
2
C bus, select a slave device with an input timing that permits use