
Rev. 2.0, 09/02, page 5 of 732
1.3
Pin Arrangement
84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
PD12/D12/
Vss
PD13/D13/AUDMD
*
4
PD14/D14/AUDCK
*
4
PD15/D15/
PA0/RXD0
PA1/TXD0
PA2/SCK0/
PA3/RXD1
PA4/TXD1
PA5/SCK1/
PA6/TCLKA/
PA7/TCLKB/
PA8/TCLKC/
PA9/TCLKD/
PA10/
PA11/
Vss
PA12/
Vcc
PA13/
*
4
*
4
/
/
PA14/
Vss(DBGMD
*
3
)
PB9/
PB8/
PB7/
PB6/
/A21/
/A20/
/A19/
/A18/
P
P
V
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
V
P
V
P
/
/
P
/
/
P
/
*
2
P
/
P
P
P
P
M
M
V
*
1
)
N
M
E
M
X
V
P
P
P
P
P
V
P
P
P
V
P
*
4
P
*
4
P
*
4
P
*
4
PE0/TIOC0A/
/TMS
*
4
PE1/TIOC0B/DRAK0/
PE2/TIOC0C/
PE3/TIOC0D/DRAK1/TDO
*
4
PE4/TIOC1A/RXD3/TCK
*
4
*
4
/TDI
*
4
Vss
PF0/AN0
PF1/AN1
PF2/AN2
PF3/AN3
PF4/AN4
PF5/AN5
AVss
PF6/AN6
PF7/AN7
AVcc
Vss
PE5/TIOC1B/TXD3
Vcc
PE6/TIOC2A/SCK3
PE7/TIOC2B/RXD2
PE8/TIOC3A/SCK2
PE9/TIOC3B/SCK3
PE10/TIOC3C/TXD2
Vss
PE11/TIOC3D/RXD3
PE12/TIOC4A/TXD3
PE13/TIOC4B/
QFP-112
(Top view)
Notes : 1. Fixed as Vcc in the Mask version, and Used as an FWP pin in the F-ZTAT version (Used as an FWE in write made).
2. Used for E10A debugging mode. Used as an
processing the
pin.
3. Used for E10A debugging mode. Fixed to Vss in the mask version, or used as a DBGMD pin in the F-ZTAT version.
4. Valid only in the F-ZTAT version (invalid only in the mask version).
pin in the F-ZTAT version. Refer to the table below for
Product type
Mask version
F-ZTAT version (when using E10A)
F-ZTAT version (Not when using E10A)
Processing
Pull-up
Yes
Yes
Yes
Fixed to Vcc
Yes
No
Yes
Fixed to Vss
Yes
No
Yes
Pull-down
Yes
No
Yes
NC
No
No
No
Processing
Figure 1.3 SH7144 Pin Arrangement