
Rev. 2.0, 09/02, page 351 of 732
12.3.1
Timer Counter (TCNT)
TCNT is an 8-bit readable/writable upcounter. When the timer enable bit (TME) in the timer
control/status register (TCSR) is set to 1, TCNT starts counting pulses of an internal clock selected
by clock select bits 2 to 0 (CKS2 to CKS0) in TCSR. When the value of TCNT overflows
(changes from H'FF to H'00), a watchdog timer overflow signal (
WDTOVF
) or interval timer
interrupt (ITI) is generated, depending on the mode selected in the WT/
IT
bit of TCSR.
The initial value of TCNT is H
′
00.
12.3.2
Timer Control/Status Register (TCSR)
TCSR is an 8-bit readable/writable register. Its functions include selecting the clock source to be
input to TCNT, and the timer mode.
Bit
Bit Name
Initial Value
R/W
Description
7
OVF
0
R/(W)
*
1
Overflow Flag
Indicates that TCNT has overflowed in interval timer
mode. Only a write of 0 is permitted, to clear the
flag. This flag is not set in watchdog timer mode.
[Setting condition]
When TCNT overflows in interval timer mode.
[Clearing condition]
When writing 0 to this bit after reading this bit or
when writing 0 to the TME bit in interval timer
mode.
Timer Mode Select
Selects whether the WDT is used as a watchdog
timer or interval timer. When TCNT overflows, the
WDT either generates an interval timer interrupt (ITI)
or generates a
WDTOVF
signal, depending on the
mode selected.
0: Interval timer mode
Interval timer interrupt (ITI) request to the CPU
when TCNT overflows
1: Watchdog timer mode
WDTOVF
signal output externally when TCNT
overflows.
For details on the TCNT overflow in watchdog
timer mode, refer to section 12.3.3, Reset
Control/Status Register (RSTCSR).
6
WT/
IT
0
R/W