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參數(shù)資料
| 型號(hào)： | SG500DYB |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | PROC SPECIFIC CLOCK GENERATOR, PDSO28 |
| 封裝： | 0.209 INCH, SSOP-28 |
| 文件頁數(shù)： | 6/7頁 |
| 文件大?。?/td> | 92K |
| 代理商： | SG500DYB |
SG500
Low Jitter Spectrum Clock Generator for PowerPC Designs.
Approved Product
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
Rev.2.1
9/18/98
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Page 6 of 7
PCB LAYOUT SUGGESTION
This is only a layout recommendation
for best performance and lower EMI.
The designer may choose a different
approach but C3, C4, C35, C36, C37, C38, C39 and C40 (all are 0.1
f) should always be used and placed as close as
possible to their VDD pins.
Via to VDD Island
Via to GND plane
Via to VCC plane
SG500
C2
FB2
C5
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
C3
8
C7
VCC
1
FB1
C9
6.6 to 22
F
6.8 to 22
F
1
2
3
4
C1
C6
VCC
2
10
C4
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