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參數(shù)資料
| 型號(hào)： | SG500DYB |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | PROC SPECIFIC CLOCK GENERATOR, PDSO28 |
| 封裝： | 0.209 INCH, SSOP-28 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大小： | 92K |
| 代理商： | SG500DYB |
SG500
Low Jitter Spectrum Clock Generator for PowerPC Designs.
Approved Product
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
Rev.2.1
9/18/98
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Page 1 of 7
PRODUCT FEATURES
T Supports Power PC CPU’s.
T Supports simultaneous PCI and Fast PCI Buses.
T Uses external buffer to reduce EMI and Jitter
T PCI synchronous clock.
T Fast PCI synchronous clock
T Separated 3.3 volt power supplies for reduced
Jitter
T < 500 pS skew between CPU and PCI clocks
T Programmable features:
- frequency selection
- margin testing frequency increases
- Output Enable for board level testing
- CPU to PCI clock offset selection
T Independent VDD supplies for all output clocks
T 28-pin SSOP 209 mil. package
T Spread Spectrum Technology for EMI reduction
T Internal Crystal Load Capacitors for 20 pF parallel
resonant crystal support.
BLOCK DIAGRAM
FREQUENCY TABLE (MHz)
FS2
FS1
FS0
CPU
PCI
PCIF
0
90
30.0
60.0
0
1
94.5(90+5%)
31.5
63
0
1
0
66.6*
33.3*
66.6*
0
1
70(66+5%)**
35**
70**
1
0
100.0(99.6)*
33.3*
66.6*
1
0
1
105.0**
35.0**
69.9**
1
0
120.0(119.9)
30.0
60.0
1
133.0**
33.3**
66.6**
* indicates 0.5 % down spread spectrum capable
** See TEST MODE table for functional definition when
SSON is low
TEST MODE. FUNCTIONALITY NOT GUARANTEED
OVER FULL TEMPERATURE AND VOLTAGE
CONNECTION DIAGRAM
PLL2
48MHz
PLL1
OE
SSON
FS(0:2)
CPU
VDDP
VDDCPU
PCIF
PCI
REF
XIN
XOUT
REF
VDDPF
14.318
VDDA
REF
VSS
VDDC
CPU
VSS
VDDP
PCI
VSS
VDDPF
PCIF
VDDF
48M
VSS
VDDR
XIN
XOUT
VSS
VDD
FS0
FS1
FS2
VDD
VSS
NC
VSS
SSON
OE
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
VDDF
VDDR
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