
3.2 – 3.2.2
3.0 Pin Configuration
S-MOS Systems, Inc. 150 River Oaks Parkway San Jose, CA 95134 Tel: (408) 922-0200 Fax: (408) 922-0238
371-1.0
20
3.2
PIN DESCRIPTION
* Master LSI common outputs COM0–COM15 correspond to slave LSI outputs COM31–COM16.
3.2.1 Power Signals
V
DD
Connected to +5V power. Common to MPU power pin V
CC
.
V
SS
0V, connected to system GND.
V
1
–V
5
Multi-level power used to drive LCDs. Voltage specified to each LCD cell is divided by
resistors or impedance-converted by an operational amplifier before being applied. Each
voltage to be applied must be based on V
DD
, while fulfilling the following conditions:
V
DD
≥
V
1
≥
V
2
≥
V
3
≥
V
4
≥
V
5
3.2.2 System Bus Interface Signals
D
7
–D
0
8–bit, tri-state, bi-directional I/O bus. Normally, connected to the data bus of an 8–/16–
bit standard microcomputer.
A0
Input pin. Normally, the LSB of the MPU address bus is connected to this input pin to
provide data/command selection.
0: Display control data on D
7
–D
0
1: Display data on D
7
–D
0
RES
Input pin. The SED1520 can be reset or initialized by setting RES to low level (if it is
interfaced with a 68 family MPU) or high level (if with an 80 family MPU). This reset op-
eration occurs when an edge of the RES signal is sensed. The level input selects the
type of interface with the 68 or 80 family MPU:
High level: Interface with 68 family MPU
Low level:
Interface with 80 family MPU
Product name
Pin No.
74
75
96~100, 1~11
93
94
95
SED1520FOA
OSC1
OSC2
COM0~COM15*
M/S
V
4
V
1
SED1521FOA
CS
CL
SEG76~SEG61
SEG79
SEG78
SEG77
SED1520FAA
CS
CL
COM0~COM15*
M/S
V
4
V
1
SED1521FAA
CS
CL
SEG76~SEG61
SEG79
SEG78
SEG77