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參數(shù)資料
| 型號： | SDC-14585-374S |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 位置變換器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, DIP36 |
| 封裝： | DDIP-36 |
| 文件頁數(shù)： | 7/18頁 |
| 文件大小： | 202K |
| 代理商： | SDC-14585-374S |
15
Data Device Corporation
www.ddc-web.com
SDC-14580
H-05/04-0
S1
1
S2
2
S3
3
S4
4
B1
5
B2
6
B3
7
B4
8
B5
9
B6
10
B7
11
B8
12
B9
13
B10
14
B11
15
B12
16
B13
17
B14
18
36
B
35
A
34
BIT
33
INH
32
+15 V
31
-15 V
30
S
29
GND
28
+5 V
27
e
26
EM
25
EL
24
CB
23
VEL
22
B16
21
B15
20
RL
19
RH
FIGURE 25. SDC-14580 PIN LOCATIONS
TABLE 9. SDC-14580 PIN FUNCTIONS
PIN NO.
TITLE
I/O
FUNCTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
I
O
I
O
I
O
I
—
I
O
I
(S)=Synchro input; (R)=Resolver input; (X)=Direct input
(R)=Resolver input
Digital Output Bit 1 (MSB)
Digital Output Bit 2
Digital Output Bit 3
Digital Output Bit 4
Digital Output Bit 5
Digital Output Bit 6
Digital Output Bit 7
Digital Output Bit 8
Digital Output Bit 9
Digital Output Bit 10 (LSB - 10-BIT MODE)
Digital Output Bit 11
Digital Output Bit 12 (LSB - 12-BIT MODE)
Digital Output Bit 13
Digital Output Bit 14 (LSB - 14-BIT MODE)
AC Reference Input. Used to drive internal demodulator
Digital Output Bit 15
Digital Output Bit 16 (LSB - 16-BIT MODE)
Velocity. DC voltage proportional to angular velocity
Converter Busy. Indicates digital output update.
Enable LSBs. Logic 0 enables digital output bits 9-16. Logic 1 disables these bits.
Enable MSBs. Logic 0 enables digital output bits 1-8. Logic 1 disables these bits.
AC Error. Used in CT mode; e is proportional to the difference between the input angle
θ and the
digital input angle
φ (θ-φ).
Supply Voltage
Ground
Control Transformer Set. Logic 1 for normal tracking; logic 0 for CT operation. Used when AC error
(e) is needed to drive external control loop by the difference angle of the resolver input and the dig-
ital input and for presetting the converter to a specific angle to reduce the step response time.
Supply Voltage
Inhibit. Logic 0 prevents digital output bits from changing.
Built-ln-Test. Monitors level of error (D) and will change to logic 0 if it exceeds 65 bits approx. Also
logic 0 for an over-velocity condition.
Resolution Control. Changes resolution during converter operation to 10, 12, 14, or 16 bits depen-
dent on logic level.
Resolution Control. Changes resolution during converter operation to 10, 12, 14, or 16 bits depen-
dent on Iogic level.
S1(S) S1(R) V(X)
S2(S) S2(R) +C(X)
S3(S) S3(R) +S(X)
S4(R)
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
RH
RL
B15
B16
VEL
CB
EL
EM
e
+5 V
GND
S
-15 V
+15 V
INH
BIT
A
B
TOP
VIEW
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