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參數(shù)資料
| 型號： | SC16C852VIET,115 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 8/55頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC UART DUAL W/FIFO 36TFBGA |
| 標準包裝： | 1,000 |
| 特點： | 可編程 |
| 通道數(shù)： | 2，DUART |
| FIFO's： | 128 字節(jié) |
| 規(guī)程： | RS485 |
| 電源電壓： | 2.5V |
| 帶自動流量控制功能： | 是 |
| 帶IrDA 編碼器/解碼器： | 是 |
| 帶故障啟動位檢測功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 36-TFBGA |
| 供應商設備封裝： | 36-TFBGA（3.5x3.5） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 935282518115 SC16C852VIET-G SC16C852VIET-G-ND |
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SC16C852V
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 21 January 2011
16 of 55
NXP Semiconductors
SC16C852V
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
6.10 DMA operation
The SC16C852V FIFO trigger level provides additional flexibility to the user for block
mode operation. The user can optionally operate the transmit and receive FIFOs in the
DMA mode (FCR[3]). The DMA mode affects the state of the RXRDYx and TXRDYx
Remark: DMA pins are not available on the TFBGA36 package.
[1]
Receive FIFO becomes full at 32 bytes when in normal mode. When TXINTLVL or RXINTLVL or FLWCNTH
or FLWCNTL contains any value other than 0x00 (extended mode) then the receive FIFO becomes full at
128 bytes.
[1]
Transmit FIFO becomes full at 32 byte when in normal mode. When TXINTLVL or RXINTLVL or FLWCNTH
or FLWCNTL contains any value other than 0x00 (extended mode) then the transmit FIFO becomes full at
128 byte.
6.11 Loopback mode
The internal loopback capability allows on-board diagnostics. In the Loopback mode, the
normal modem interface pins are disconnected and reconfigured for loopback internally
(see Figure 9). MCR[3:0] register bits are used for controlling loopback diagnostic testing.
In the Loopback mode, the transmitter output (TXA/TXB) and the receiver input
(RXA/RXB) are disconnected from their associated interface pins, and instead are
connected together internally. The CTSx, DSRx, CDx, and RIx are disconnected from
their normal modem control inputs pins, and instead are connected internally to RTS,
DTR, MCR[3] (OP2A/OP2B) and MCR[2] (OP1A/OP1B). Loopback test data is entered
into the transmit holding register via the user data bus interface, D[7:0]. The transmit
UART serializes the data and passes the serial data to the receive UART via the internal
loopback connection. The receive UART converts the serial data back into parallel data
that is then made available at the user data interface D[7:0]. The user optionally compares
the received data to the initial transmitted data for verifying error-free operation of the
UART TX/RX circuits.
In this mode the interrupt pins are 3-stated, therefore the software must use polling
method (see Section 7.2.2) to send and receive data.
Table 7.
Effect of DMA mode on state of RXRDYx pin
Non-DMA mode
DMA mode
1 = FIFO empty
0-to-1 transition when FIFO empties
0 = at least 1 byte in FIFO 1-to-0 transition when FIFO reaches trigger level, or time-out occurs[1]
Table 8.
Effect of DMA mode on state of TXRDYx pin
Non-DMA mode
DMA mode
1 = at least 1 byte in FIFO 0-to-1 transition when FIFO becomes full [1]
0 = FIFO empty
1-to-0 transition when FIFO has at least one empty location
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相關代理商/技術(shù)參數(shù) |
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|---|---|
| SC16C852VIET-G | 功能描述:UART 接口集成電路 1.8V 2CH UART 128B FIFO 5MBPS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16C852VIET-S | 功能描述:UART 接口集成電路 1.8V 2CH UART 128B FIFO 5MBPS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16DP-26 | 制造商:Thomas & Betts 功能描述:SAXXIT CABLE CLIP W/ DRIVE PIN -7 制造商:Belden Inc 功能描述: |
| SC16DP-3Q | 制造商:Thomas & Betts 功能描述:SAXXIT CABLE CLIP W/ DRIVE PIN -8 |
| SC16-FM-M16-NPB-ML-1 | 制造商:HellermannTyton 功能描述: |
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