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參數(shù)資料
| 型號(hào)： | SAB80C517A-N18-T3 |
| 廠商： | SIEMENS A G |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-Bit CMOS Single-Chip Microcontroller |
| 中文描述： | 8-BIT, 18 MHz, MICROCONTROLLER, PQCC84 |
| 文件頁數(shù)： | 52/77頁 |
| 文件大?。?/td> | 1358K |
| 代理商： | SAB80C517A-N18-T3 |
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SAB 80C517A/83C517A-5
Semiconductor Group
51
1994-05-01
The status of all output lines of the controller can be looked up in table 8.
Hardware Power Down Mode without affecting the low power consumption.
level (inactive state) an automatic start up procedure is performed:
oscillator starts up very fast (typ. less than 2 microseconds).
the part from reset with oscillator watchdog status flag not set.
reset function. (Thus, pin Reset has to be inactive during Hardware Power Down Mode).
Power Down Mode
The power down mode is entered by two consecutive instructions directly following each other.
The first instruction has to set the flag PDE (power down enable) and must not set PDS (power
down set). The following instruction has to set the start bit PDS. Bits PDE and PDS will
automatically be cleared after having been set.
The instruction that sets bit PDS is the last instruction executed before going into power down
mode. The only exit from power down mode is a hardware reset.
Hardware Controlled Power Down Mode
The pin HWPD controls this mode. If it is on logic high level (inactive) the part is running in the
normal operating modes. If pin HWPD gets active (low level) the part enters the Hardware
Power Down Mode; this is independent of the state of pin PE/SWD.
HWPD is sampled once per machine cycle. If it is found active, the device starts a complete
internal reset sequence. The watchdog timer is stopped and its status flag WDTS is cleared
exactly the same effects as a hardware reset. In this phase the power consumption is not yet
reduced. After completion of the internal reset both oscillators of the chip are disabled. At the
same time the port pins and several control lines enter a floating state as shown in table 8. In
this state the power consumption is reduced to the power down current IPD. Also the supply
voltage can be reduced. Table 8 also lists the voltages which may be applied at the pins during
Termination of HWPD Mode:
This power down state is maintained while pin HWPD is held active. If HWPD goes to high
– First the pins leave their floating condition and enter their default reset state
(as they had immediately before going to float state).
– Both oscillators are enabled (only if OWE = high). The oscillator watchdog’s RC
oscillator starts up very fast (typ. less than 2 microseconds)
– Because the oscillator watchdog is active it detects a failure condition if the
on-chip oscillator hasn’t yet started. Hence, the watchdog keeps the part in reset
and supplies the internal clock from the RC oscillator.
– Finally, when the on-chip oscillator has started, the oscillator watchdog releases
When automatic start of the watchdog was enabled (PE/SWD connected to
V
CC
)
,
the Watchdog Timer will start, too (with its default reload value for time-out period).
– The Reset pin overrides the Hardware Power Down function, i.e. if reset gets active
during Hardware Power Down it is terminated and the device performs the normal
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