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參數(shù)資料
| 型號： | SAB80C517A-N18-T3 |
| 廠商： | SIEMENS A G |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-Bit CMOS Single-Chip Microcontroller |
| 中文描述： | 8-BIT, 18 MHz, MICROCONTROLLER, PQCC84 |
| 文件頁數(shù)： | 50/77頁 |
| 文件大?。?/td> | 1358K |
| 代理商： | SAB80C517A-N18-T3 |
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SAB 80C517A/83C517A-5
Semiconductor Group
49
1994-05-01
Power Saving Modes
The SAB 80C517A provides – due to Siemens ACMOS technology – four modes in which pow-
er consumption can be significantly reduced.
– The
Slow Down Mode
The controller keeps up the full operating functionality, but is driven with one eighth
of its normal operating frequency. Slowing down the frequency remarkable reduces
power consumption.
– The
Idle Mode
The CPU is gated off from the oscillator, but all peripherals are still supplied with the
clock and continue working.
– The
Power Down Mode
Operation of the SAB 80C517A is stopped, the on-chip oscillator and the RC-oscillator
are turned off. This mode is used to save the contents of the internal RAM with a very
low standby current.
–
The Hardware Power Down Mode
Operation of the SAB 80C517A is stopped, the on-chip oscillator and the RC-Oscillator
are turned off. The pin HWPD controls this mode. Port pins and several control lines
enter a floating state. The Hardware Power Down Mode is independent of the state of
pin PE/SWD.
Hardware Enable for Software controlled Power Saving Modes
A dedicated Pin PE/SWD) of the SAB 80C517A allows to block the Software controlled power
saving modes. Since this pin is mostly used in noise-critical application it is combined with an
automatic start of the Watchdog Timer.
PE/SWD = V
H
(logic high level):
Using of the power saving modes is not possible.
The watchdog timer starts immediately after reset.
The instruction sequences used for entering of
power saving modes will not affect the normal operation
of the device.
PE/SWD = V
IL
(logic low level):
All power saving modes can be activated by software.
When left unconnected, Pin /PE/SWD is pulled high by a weak internal pullup. This is done to
provide system protection on default.
The logic-level applied to pin PE/SWD can be changed during program execution to allow or to
block the use of the power saving modes without any effect on the on-chip watchdog circuitry.
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