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參數(shù)資料
| 型號： | S98UAE877AKLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 98UAE SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC40 |
| 封裝： | 6 X 6 MM, LEAD FREE, PLASTIC, MLF-40 |
| 文件頁數(shù)： | 15/16頁 |
| 文件大小： | 254K |
| 代理商： | S98UAE877AKLFT |
ICS98UAE877A
1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER
COMMERCIAL TEMPERATURE GRADE
1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER
8
ICS98UAE877A
7181/3
Timing Requirements Over Recommended Operating Free-Air Temperature
Range
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = 0°C to +70°C, Industrial: TA = -40°C to +85°C; Supply Voltage AVDD/VDDQ = 1.5V ± 0.075V.
Symbol
Parameter1
1
The PLL must be able to handle spread spectrum induced skew.
Conditions
Min.
Max.
Units
freqOP
Max Clock Frequency2
2
Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is
not required to meet the other timing parameters. (Used for low speed system debug.)
1.5V ± 0.075V @ 25
° C95
410
MHz
freqAPP
Application Frequency Range3
3
Application clock frequency indicates a range over which the PLL must meet all timing parameters.
1.5V ± 0.075V @ 25
° C160
410
MHz
dTIN
Input Clock Duty Cycle
40
60
%
TSTAB
CLK Stabilization4
4
Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback
signal to its reference signal, within the value specificied by the Static Phase Offset (t
), after power-up.
During normal operation, the stabilization time is also the time required for the integrated PLL circuit to ob-
tain phase lock of its feedback signal to its reference signal when CLK and CLK go to a logic low state,
enter the power-down mode and later return to active operation. CLK and CLK may be left floating after
they have been driven low for one complete clock cycle.
9
s
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