參數(shù)資料
型號(hào)： S29GL128P10TFIR10
廠商： SPANSION LLC
元件分類： PROM
英文描述： 3.0 Volt-only Page Mode Flash Memory featuring 90 nm MirrorBit Process Technology
中文描述： 128M X 1 FLASH 3V PROM, 100 ns, PDSO56
封裝： 20 X 14 MM, LEAD FREE, MO-142EC, TSOP-56
文件頁數(shù)： 74/80頁
文件大?。?/td> 2706K
代理商： S29GL128P10TFIR10
76
S29GL-P MirrorBit Flash Family
S29GL-P_00_A12 November 20, 2009
Da ta
Sh e e t
13. Advance Information on S29GL-R 65 nm MirrorBit Hardware
Reset (RESET#) and Power-up Sequence
Note
CE#, OE# and WE# must be at logic high during Reset Time.
Figure 13.1 Reset Timings
Note
The sum of tRP and tRH must be equal to or greater than tRPH.
Notes
1. VIO < VCC + 200 mV.
2. VIO and VCC ramp must be in sync during power-up. If RESET# is not stable for 300 s, the following conditions may occur: the device
does not permit any read and write operations, valid read operations return FFh, and a hardware reset is required.
3. Maximum VCC power up current is 20 mA (RESET# =VIL).
Figure 13.2 Power-On Reset Timings
Note
The sum of tRP and tRH must be equal to or greater than tRPH.
Table 13.1 Hardware Reset (RESET#)
Parameter
Description
Limit
Time
Unit
tRPH
RESET# Low to CE# Low
Min
35
s
tRP
RESET# Pulse Width
Min
200
ns
tRH
Time between RESET# (high) and CE# (low)
Min
200
ns
Table 13.2 Power-Up Sequence Timings
Parameter
Description
Limit
Time
Unit
tVCS
VCC Setup Time to first access
Min
300
s
tVIOS
VIO Setup Time to first access
Min
300
s
tRPH
RESET# Low to CE# Low
Min
35
s
tRP
RESET# Pulse Width
Min
200
ns
tRH
Time between RESET# (high) and CE# (low)
Min
200
ns
tRPH
CE#
RESET#
tRP
tRH
CE#
VCC
V IO
RESET#
t VIOS
t VCS
t RP
t RH
t RPH
相關(guān)PDF資料
PDF描述
S29GL128P10TFIV10 3.0 Volt-only Page Mode Flash Memory featuring 90 nm MirrorBit Process Technology
S29GL032N90BFI32 2M X 16 FLASH 3V PROM, 90 ns, PBGA48
S2A SURFACE MOUNT RECTIFIER
S2B SURFACE MOUNT RECTIFIER
S2C1R-1-5-H 4000 MHz - 8000 MHz RF/MICROWAVE SGL POLE DOUBLE THROW SWITCH, 1.7 dB INSERTION LOSS
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