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參數(shù)資料
| 型號(hào)： | S29GL01GP12FACR13 |
| 廠商： | SPANSION LLC |
| 元件分類： | PROM |
| 英文描述： | 1G X 1 FLASH 3V PROM, 120 ns, PBGA64 |
| 封裝： | 13 X 11 MM, 1 MM PITCH, FBGA-64 |
| 文件頁(yè)數(shù)： | 60/80頁(yè) |
| 文件大?。?/td> | 2706K |
| 代理商： | S29GL01GP12FACR13 |
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November 20, 2009 S29GL-P_00_A12
S29GL-P MirrorBit Flash Family
63
Data
She e t
Figure 11.11 Chip/Sector Erase Operation Timings
Notes
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see Write Operation Status on page 36.)
2. These waveforms are for the word mode
Figure 11.12 Data# Polling Timings (During Embedded Algorithms)
Notes
1. VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.
2. tOE for data polling is 45 ns when VIO = 1.65 to 2.7 V and is 35 ns when VIO = 2.7 to 3.6 V
3. CE# does not need to go high between status bit reads
OE#
CE#
Addresses
VCC
WE#
Data
2AAh
SA
tAH
tWP
tWC
tAS
tWPH
555h for chip erase
10 for Chip Erase
30h
tDS
tVCS
tCS
tDH
55h
tCH
In
Progress
Complete
tWHWH2
VA
Erase Command Sequence (last two cycles)
Read Status Data
RY/BY#
tRB
tBUSY
WE#
CE#
OE#
High Z
tOE
High Z
DQ7
DQ6–DQ0
RY/BY#
tBUSY
Complement
True
Addresses
VA
tOEH
tCE
tCH
tOH
tDF
VA
Status Data
Complement
Status Data
True
Valid Data
tACC
tRC
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