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| 型號(hào)： | S29GL01GP12FACR13 |
| 廠商： | SPANSION LLC |
| 元件分類(lèi)： | PROM |
| 英文描述： | 1G X 1 FLASH 3V PROM, 120 ns, PBGA64 |
| 封裝： | 13 X 11 MM, 1 MM PITCH, FBGA-64 |
| 文件頁(yè)數(shù)： | 3/80頁(yè) |
| 文件大?。?/td> | 2706K |
| 代理商： | S29GL01GP12FACR13 |
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November 20, 2009 S29GL-P_00_A12
S29GL-P MirrorBit Flash Family
11
Data
She e t
2.
Input/Output Descriptions & Logic Symbol
Table 2.1 identifies the input and output package connections provided on the device.
Table 2.1 Input/Output Descriptions
Symbol
Type
Description
A25–A0
Input
Address lines for GL01GP
A24–A0 for GL512P
A23–A0 for GL256P,
A22–A0 for GL128P.
DQ14–DQ0
I/O
Data input/output.
DQ15/A-1
I/O
DQ15: Data input/output in word mode.
A-1: LSB address input in byte mode.
CE#
Input
Chip Enable.
OE#
Input
Output Enable.
WE#
Input
Write Enable.
VCC
Supply
Device Power Supply.
VIO
Supply
Versatile IO Input.
VSS
Supply
Ground.
NC
No Connect
Not connected internally.
RY/BY#
Output
Ready/Busy. Indicates whether an Embedded Algorithm is in progress or complete. At
VIL, the device is actively erasing or programming. At High Z, the device is in ready.
BYTE#
Input
Selects data bus width. At VIL, the device is in byte configuration and data I/O pins DQ0-
DQ7 are active and DQ15/A-1 becomes the LSB address input. At VIH, the device is in
word configuration and data I/O pins DQ0-DQ15 are active.
RESET#
Input
Hardware Reset. Low = device resets and returns to reading array data.
WP#/ACC
Input
Write Protect/Acceleration Input. At VIL, disables program and erase functions in the
outermost sectors. At VHH, accelerates programming; automatically places device in
unlock bypass mode. Should be at VIH for all other conditions. WP# has an internal pull-
up; when unconnected, WP# is at VIH.
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