參數(shù)資料
型號(hào)： S1C60N09D
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 0.08 MHz, MICROCONTROLLER, UUC70
封裝： DIE-70
文件頁(yè)數(shù)： 8/62頁(yè)
文件大?。?/td> 476K
代理商： S1C60N09D
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)
10
EPSON
S1C60N09 TECHNICAL MANUAL
Table 4.1.1 I/O memory map
Address
Comment
D3
D2
Register
D1
D0
Name
Init 1
10
073H
K03
K02
K01
K00
R
K03
K02
K01
K00
– 2
High
Low
Input port data (K00–K03)
071H
SWL3
SWL2
SWL1
SWL0
R
SWL3
SWL2
SWL1
SWL0
0
MSB
Stopwatch timer 1/100 sec data (BCD)
LSB
072H
SWH3
SWH2
SWH1
SWH0
R
SWH3
SWH2
SWH1
SWH0
0
MSB
Stopwatch timer 1/10 sec data (BCD)
LSB
070H
TM3
TM2
TM1
TM0
R
TM3
TM2
TM1
TM0
0
Clock timer data (2 Hz)
Clock timer data (4 Hz)
Clock timer data (8 Hz)
Clock timer data (16 Hz)
075H
EIK03
EIK02
EIK01
EIK00
R/W
EIK03
EIK02
EIK01
EIK00
0
Enable
Mask
Interrupt mask register (K00–K03)
076H
HLMOD
0
EISWIT1 EISWIT0
R/W
R
R/W
HLMOD
0 3
EISWIT1
EISWIT0
0
– 2
0
Heavy load
–
Enable
Normal
–
Mask
Heavy load protection mode register
Unused
Interrupt mask register (stopwatch 1 Hz)
Interrupt mask register (stopwatch 10 Hz)
07EH
TMRST SWRUN SWRST
IOC0
W
R/W
W
R/W
TMRST3
SWRUN
SWRST3
IOC0
Reset
0
Reset
0
Reset
Run
Reset
Output
–
Stop
–
Input
Clock timer reset
Stopwatch timer Run/Stop
Stopwatch timer reset
I/O control register 0 (P00–P03)
078H
CSDC
ETI2
ETI8
ETI32
R/W
CSDC
ETI2
ETI8
ETI32
0
Static
Enable
Dynamic
Mask
LCD drive switch
Interrupt mask register (clock timer 2 Hz)
Interrupt mask register (clock timer 8 Hz)
Interrupt mask register (clock timer 32 Hz)
0FFH
0
LCDON
R
R/W
0 3
LCDON
– 2
1
–
On
–
Off
Unused
LCD display On/Off control
079H
0
TI2
TI8
TI32
R
0 3
TI2 4
TI8 4
TI32 4
– 2
0
–
Yes
–
No
Unused
Interrupt factor flag (clock timer 2 Hz)
Interrupt factor flag (clock timer 8 Hz)
Interrupt factor flag (clock timer 32 Hz)
07AH
0
IK0
SWIT1
SWIT0
R
0 3
IK0 4
SWIT1 4
SWIT0 4
– 2
0
–
Yes
–
No
Unused
Interrupt factor flag (K00–K03)
Interrupt factor flag (stopwatch 1 Hz)
Interrupt factor flag (stopwatch 10 Hz)
07CH
R03
R02
R01
R00
R/W
R03
R02
R01
R00
0
High
Low
Output port (R03, BZ)
Output port (R02, FOUT)
Output port (R01)
Output port (R00, BZ)
07DH
P03
P02
P01
P00
R/W
P03
P02
P01
P00
– 2
High
Low
I/O port data (P00–P03)
Output latch is reset at initial reset
0FEH
0
IOC1
R
R/W
0 3
IOC1
– 2
0
–
Output
–
Input
Unused
I/O control register 1 (P10–P13)
0FDH
P13
P12
P11
P10
R/W
P13
P12
P11
P10
– 2
High
Low
I/O port data (P10–P13)
Output latch is reset at initial reset
1
2
Initial value at initial reset
Not set in the circuit
3
4
Always "0" being read
Reset (0) immediately after being read
0F6H
BZFQ
0
R/W
R
BZFQ
0 3
0
– 2
2 kHz
–
4 kHz
–
Buzzer frequency selection
Unused
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