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參數(shù)資料
| 型號： | S1C60L09D |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 0.08 MHz, MICROCONTROLLER, UUC70 |
| 封裝： | DIE-70 |
| 文件頁數(shù)： | 40/62頁 |
| 文件大?。?/td> | 476K |
| 代理商： | S1C60L09D |
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)
S1C60N09 TECHNICAL MANUAL
EPSON
39
4.10 Interrupt and HALT
The S1C60N09 Series provides the following interrupt settings, each of which is maskable.
External interrupt:
Input port interrupt (one)
Internal interrupt:
Timer interrupt (three)
Stopwatch interrupt (two)
To enable interrupts, the interrupt flag must be set to "1" (EI) and the necessary related interrupt mask
registers must be set to "1" (enable). When an interrupt occurs, the interrupt flag is automatically reset to
"0" (DI) and interrupts after that are inhibited.
Figure 4.10.1 shows the configuration of the interrupt circuit.
K00
EIK00
K01
EIK01
K02
EIK02
K03
EIK03
SWIT0
EISWIT0
SWIT1
EISWIT1
TI2
ETI2
TI8
ETI8
TI32
ETI32
IK0
(MSB)
:
(LSB)
Program counter
(low-order 4 bits)
Interrupt vector
Interrupt factor flag
Interrupt mask register
Interrupt
flag
INT
(Interrupt request)
Fig. 4.10.1 Configuration of interrupt circuit
HALT mode
When the HALT instruction is executed, the CPU stops operating and enters the HALT mode. The
oscillation circuit and the peripheral circuits operate in the HALT mode. By an interrupt, the CPU exits
the HALT mode and resumes operating.
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