參數(shù)資料
型號： S1C60L09D
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 0.08 MHz, MICROCONTROLLER, UUC70
封裝： DIE-70
文件頁數(shù)： 32/62頁
文件大小： 476K
代理商： S1C60L09D
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)
32
EPSON
S1C60N09 TECHNICAL MANUAL
4.7.3 I/O memory of clock timer
Table 4.7.3.1 shows the clock timer control bits and their addresses.
Table 4.7.3.1 Control bits of clock timer
Address
Comment
D3
D2
Register
D1
D0
Name
Init 1
10
070H
TM3
TM2
TM1
TM0
R
TM3
TM2
TM1
TM0
0
Clock timer data (2 Hz)
Clock timer data (4 Hz)
Clock timer data (8 Hz)
Clock timer data (16 Hz)
07EH
TMRST SWRUN SWRST
IOC0
WR/W
TMRST3
SWRUN
SWRST3
IOC0
Reset
0
Reset
0
Reset
Run
Reset
Output
–
Stop
–
Input
Clock timer reset
Stopwatch timer Run/Stop
Stopwatch timer reset
I/O control register 0 (P00–P03)
078H
CSDC
ETI2
ETI8
ETI32
R/W
CSDC
ETI2
ETI8
ETI32
0
Static
Enable
Dynamic
Mask
LCD drive switch
Interrupt mask register (clock timer 2 Hz)
Interrupt mask register (clock timer 8 Hz)
Interrupt mask register (clock timer 32 Hz)
079H
0
TI2
TI8
TI32
R
0 3
TI2 4
TI8 4
TI32 4
– 2
0
–
Yes
–
No
Unused
Interrupt factor flag (clock timer 2 Hz)
Interrupt factor flag (clock timer 8 Hz)
Interrupt factor flag (clock timer 32 Hz)
1
2
Initial value at initial reset
Not set in the circuit
3
4
Always "0" being read
Reset (0) immediately after being read
TM0–TM3: Timer data (070H)
The l6 Hz to 2 Hz timer data of the clock timer can be read from this register. These four bits are read-
only, and write operations are invalid.
After an initial reset, the timer data is initialized to "0H".
ETI32, ETI8, ETI2: Interrupt mask registers (078HD0–D2)
These registers are used to mask the clock timer interrupt.
When "1" is written: Enabled
When "0" is written: Masked
Reading: Valid
The interrupt mask registers (ETI32, ETI8, ETI2) mask the corresponding interrupt frequencies (32 Hz, 8
Hz, 2 Hz).
At initial reset, these registers are all set to "0".
TI32, TI8, TI2: Interrupt factor flags (079HD0–D2)
These flags indicate the status of the clock timer interrupt.
When "1" is read: Interrupt has occurred
When "0" is read: Interrupt has not occurred
Writing: Invalid
The interrupt factor flags (TI32, TI8, TI2) correspond to the clock timer interrupts (32 Hz, 8 Hz, 2 Hz). The
software can determine from these flags whether there is a clock timer interrupt. However, even if the
interrupt is masked, the flags are set to "1" at the falling edge of the signal. These flags can be reset when
the register is read by the software.
Reading of interrupt factor flags is available at EI, but be careful in the following cases.
If the interrupt mask register value corresponding to the interrupt factor flag to be read is set to "1", an
interrupt request will be generated by the interrupt factor flag set timing, or an interrupt request will not
be generated. Be very careful when interrupt factor flags are in the same address.
At initial reset, these flags are set to "0".
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