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參數(shù)資料
| 型號： | S-4561A |
| 廠商： | Seiko Instruments Inc. |
| 英文描述： | LCD Controller-Driver With Built-in Serial and Parallel interfaces(內(nèi)置串行和并行接口的LCD控制器-驅(qū)動器) |
| 中文描述： | LCD控制器，內(nèi)置的串行和并行接口（內(nèi)置串行和并行接口的液晶顯示控制器-驅(qū)動器驅(qū)動程序） |
| 文件頁數(shù)： | 8/49頁 |
| 文件大小： | 461K |
| 代理商： | S-4561A |
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LCD Controller-Driver
S-4561A
Seiko Instruments Inc.
7
Table 8 Chip Identification Mark Coordinates
Chip Identification
Mark
A
B
X-Coordinates
Y-Coordinates
- 3660
3669
625
- 590
I
Function Explanation
1.
Interface
Serial and parallel interfaces are built in. Either one can be selected by changing over the P/SX terminal. The parallel
interface can respond to both 4- and 8-bit parallel data transmission. Namely, data is transmitted once in the 8-bit interface
or twice in the 4-bit interface. The CPU interfaces with respective instruction codes and several kinds of data via the
instruction decoder and the data holder.
Data is read from each memory via the data holder. Through the ADDRESS SETTING Command, the contents of the
memory are read once into the data holder, and are output through the next READ command. Then, the next data is read
into the data holder.
Parallel and serial interfaces execute and finish all instructions within the Enable or Clock cycle specified in accordance with
timing characteristics. Because the
“
BUSY
”
state is cleared within the cycle time, instructions can be executed in succession
without confirming the
“
BUSY.
”
1.1 Parallel Interface
The parallel interface is engaged when the P/SX terminal is
“
H.
”
Connect and fix the P/SX terminal to VDD.
Table 9 Interface
Figure 3 8-Bit Length Parallel Interface (68-Family CPU)
Figure 4 8-Bit Length Parallel Interface (80-Family CPU)
Pin Name
RS
E
R/WX
DB(7:0)
C86=0: 80-Family MPU
RS
RD
WR
DB(7:0)
C86=1: 68-Family MPU
RS
E
R/WX
DB(7:0)
RS
E
R/WX
DB0 to DB7
[Example: 8-Bit Length Parallel Interface] (68-Family CPU)
Instruction
Data Write
Address
Data
Instruction
Write
Data
Write
Address
Read
Data
Read
RS
E (RD)
R/WX (WR)
DB0 to DB7
[Example: 8-Bit Length Parallel Interface] (80-Family CPU)
Instruction
Data Write
Address
Data
Write
Instruction
Data
Write
Address
Read
Data
Read
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