參數(shù)資料
型號(hào)： S-4525BA
廠商： Seiko Instruments Inc.
英文描述： Dot Matrix LCD Driver(點(diǎn)陣LCD驅(qū)動(dòng)器)
中文描述： 點(diǎn)陣LCD驅(qū)動(dòng)器（點(diǎn)陣液晶驅(qū)動(dòng)器）
文件頁(yè)數(shù)： 8/23頁(yè)
文件大?。?/td> 166K
代理商： S-4525BA
DOT MATRIX LCD DRIVER
S-4525BA
Seiko Instruments Inc.
7
4. Status
The internal operation status of S-4525BA is monitored for four kinds of status. The status is output in D
4
through D
7
. For the monitoring method and function, refer to the Command functions section.
Table 10
Item
Output pin
D
7
D
6
D
5
Status
Busy flag
ADC select
Display
ON/OFF
Reset
“1”: Command operation, Reset operation “0”: Command ready
“1”:
Forward
“1”: Display all-lit
“0”: Reverse
“0”: Normal display status
D
4
“1”: Resetting
“0”: Normal operation status
5. Busy flag
During internal operation, for example command operation, the busy flag is “1”, and commands other than
Status Read are not received. The Busy flag is output in D7 through the Status Read command. When
accessing the S-4525BA by the signal which specifies the value of read cycle and write cycle timing, the busy
flag “0” is not required to be confirmed.
6. Data bus
Table 11
68 family
R/WX
80 family
RDX
0
1
0
1
Operation
WRX
1
0
1
0
1
1
0
0
1
0
1
0
Read from Display Data RAM
Write to Display Data RAM
Status Read
Command Read to internal register
7. Display Data RAM
The S-4525BA has Display Data RAM (8 bits X 4 pages X 80 columns=2560 bits). As the memory area for
display, 8 bits X 4 pages X 61 columns (segments)=1952 bits is valid. It is possible to use the not-used area for
display as normal SRAM. The Display Data RAM is in dual port RAM and enables access from the MPU
through Page address and Column address. To the LCD driver side, the one line’s common output is read by
Line address. The correspondence between Page address, Column address, and Line address is shown in
Figure 6.
Display data reading /writing from/to the MPU interface and display data reading to the LCD display are
executed independently; one is executed through command, the other is executed synchronizing with the LCD
display clock.
At power-on, the display RAM data is not fixed. After power-on, clear the display RAM or write the display data
with display OFF and turn the display ON.
8. Reading and writing of display data
The S-4525BA reads and writes the display data through the internal bus holder. The display data is read to the
bus holder from the display data RAM, and in the next read cycle on the data bus. Therefore, a dummy read
cycle is needed before the first read cycle. When reading the display data after the address set and the data
write cycle, a dummy read is needed. Since the reading of the display data is executed using this bus holder, it
is possible to read the data at high speed.
Display data is written to the display data RAM through the bus holder within a write cycle. Therefore, writing the
display data does not need a dummy cycle.
9. Column address
The column address of the display data RAM is that for writing and reading of the display data. Setting the
column address is executed through a command. When accessing the display data RAM from the MPU, the
address is incremented by one.
A
0
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