參數(shù)資料
型號(hào)： S-29630A
廠商： Seiko Instruments Inc.
英文描述： 32Kbit Serial EEPROM(32K位串行EEPROM)
中文描述： 32Kbit串行EEPROM（32K的位串行EEPROM的）
文件頁(yè)數(shù)： 8/44頁(yè)
文件大?。?/td> 178K
代理商： S-29630A
CMOS SERIAL E
2
PROM
S-29530A / 29630A
7
2. Write (WRITE, ERASE)
There are two write instructions, WRITE and ERASE. Each automatically begins writing to the non-volatile memory
when CS goes low at the completion of the specified clock input.
The write operation is completed in 10 ms (t
PR
Max.), and the typical write period is less than 4 ms. In the S-29530A /
630A series, it is easy to VERIFY the completion of the write operation in order to minimize the write cycle by setting CS to
high and checking the DO pin, which is low during the write operation and high after its completion. This VERIFY
procedure can be executed over and over again. There are two methods to detect a change in the DO output. One is to
detect a change from low to high setting CS to high, and the other is to detect a change from low to high as a result of
repetitious operations of returning the CS to low after setting CS to high and checking the DO output.
Because all SK and DI inputs are ignored during the write operation, any input of instruction will also be disregarded.
When DO outputs high after completion of the write operation or if it is in the high-impedence state (Hi-Z), the input of
instructions is available. Even if the DO pin remains high, it will enter the high-impedence state upon the recognition of a
high of DI (start-bit) attached to the rising edge of an SK pulse. (see Figure 3).
DI input should be low during the VERIFY procedure.
2.1 WRITE
This instruction writes 16-bit data to a specified address.
After changing CS to high, input a start-bit, op-code (WRITE), address, and 16-bit data. If there is a data overflow of
more than 16 bits, only the last 16-bits of the data is considered valid. Changing CS to low will start the WRITE operation.
It is not necessary to make the data "1" before initiating the WRITE operation.
A9
A8
5
6
7
8
9
10
11
12
13
14
4
A7
A6
A5
A4
A3
A2
A1
A0
D15
t
CDS
t
PR
busy
Hi-Z
t
SV
VERIFY
Hi-Z
CS
t
HZ1
29
D0
ready
1
DI
2
3
0
1
SK
DO
Figure 6
Write Timing (S-29530A)
5
6
7
8
9
10
11
12
13
14
4
15
16
A9
A8
A7
A6
A5
A4
A3
A2
A1
X
A10
A0
D15
t
CDS
t
PR
busy
Hi-Z
t
SV
VERIFY
Hi-Z
CS
t
HZ1
31
D0
ready
1
DI
2
3
0
1
SK
DO
Figure 7
Write Timing (S-29630A)
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