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參數資料
| 型號： | S-29630A |
| 廠商： | Seiko Instruments Inc. |
| 英文描述： | 32Kbit Serial EEPROM(32K位串行EEPROM) |
| 中文描述： | 32Kbit串行EEPROM（32K的位串行EEPROM的） |
| 文件頁數： | 7/44頁 |
| 文件大小： | 178K |
| 代理商： | S-29630A |
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CMOS SERIAL E
2
PROM
S-29530A / 29630A
6
Operation
A2
A8
12
47
31
14
D15
D15 D14
D14 D13
D14
Hi-Z
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
+1
D13
D0
D1
D2
D15
0
Hi-Z
A3
A4
A5
A6
A7
A9
0
1
1
30
29
28
27
26
11
10
9
8
7
6
5
4
3
2
1
46
45
44
43
42
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
+2
D13
D0
D1
D2
13
CS
SK
DI
DO
16
15
A1
A0
Figure 4
Read Timing (S-29530A)
15
A2
A8
12
50
49
48
14
D15
D13
D14
D12
D13
D14
Hi-Z
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
+1
D14
D15
D0
D15
0
Hi-Z
A3
A4
A5
A6
A7
A9
0
1
1
34
33
32
31
11
10
9
8
7
6
5
4
3
2
1
47
46
45
44
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
+2
D13
D0
D1
D2
13
CS
SK
DI
DO
16
A1
A0
A10
X
18
17
19
Figure 5
Read Timing (S-29630A)
Instructions (in the order of start-bit, instruction, address, and data) are latched to DI in synchronization with the rising
edge of SK after CS goes high. A start-bit can only be recognized when the high of DI is latched to the rising edge of SK
when CS goes from low to high, it is impossible for it to be recognized as long as DI is low, even if there are SK pulses
after CS goes high. Any SK pulses input while DI is low are called "dummy clocks." Dummy clocks can be used to
adjust the number of clock cycles needed by the serial IC to match those sent out by the CPU. Instruction input finishes
when CS goes low, where it must be low between commands during t
CDS
.
All input, including DI and SK signals, is ignored while CS is low, which is stand-by mode.
1. Read
The READ instruction reads data from a specified address. After A0 is latched at the rising edge of SK, DO output
changes from a high-impedance state (Hi-Z) to low level output. Data is continuously output in synchronization with the
rise of SK.
When all of the data (D15 to D0) in the specified address has been read, the data in the next address can be read
with the input of another SK clock. Thus, it is possible for all of the data addresses to be read through the continuous
input of SK clocks as long as CS is high.
The last address (An
A1 A0 = 1
11) rolls over to the top address (An
A1 A0 = 0
00).
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相關代理商/技術參數 |
參數描述 |
|---|---|
| S2974320530100200 | 制造商:MILL-MAX 功能描述: |
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| S299-10-316-00-080200 | 制造商:Mill-Max Mfg Corp 功能描述: |
| S29AL004D | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:4 Megabit (512 Kx 8-Bit/256 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
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