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參數(shù)資料
| 型號： | RX5500 |
| 廠商： | RF Monolithics, Inc. |
| 英文描述： | 433.92 MHz Hybrid Receiver |
| 中文描述： | 433.92兆赫混合接收機(jī) |
| 文件頁數(shù)： | 8/10頁 |
| 文件大?。?/td> | 89K |
| 代理商： | RX5500 |
Pin
Name
Description
1
GND1
GND1 is the RF ground pin. GND2 and GND3 should be connected to GND1 by short, low-inductance traces.
2
VCC1
VCC1 is the positive supply voltage pin for the receiver base-band circuitry. VCC1 must be bypassed by an RF
capacitor, which may be shared with VCC2. See the description of VCC2 (Pin 16) for additional information.
3
RFA1
RFA1 enables the high gain mode of the first RF amplifier. This pin is normally connected to VCC1.
4
NC
This pin should be left unconnected.
5
BBOUT
BBOUT is the receiver base-band output pin. This pin drives the CMPIN pin through a coupling capacitor C
BBO
for
internal data slicer operation. The time constant t
BBC
for this connection is:
t
BBC
= 0.064*C
BBO
, where t
BBC
is in μs and C
BBO
is in pF
A ±10% ceramic capacitor should be used between BBOUT and CMPIN. The time constant can vary between t
BBC
and 1.8*t
BBC
with variations in supply voltage, temperature, etc. The optimum time constant in a given circum-
stance will depend on the data rate, data run length, and other factors as discussed in the
ASH Transceiver De-
signer’s Guide
. A common criteria is to set the time constant for no more than a 20% voltage droop during SP
MAX
.
For this case:
C
BBO
= 70*SP
MAX
, where SP
MAX
is the maximum signal pulse width in μs and C
BBO
is in pF
The output from this pin can also be used to drive an external data recovery process (DSP, etc.). The nominal out-
put impedance of this pin is 1 K. When the receiver RF amplifiers are operating at a 50%-50% duty cycle, the
BBOUT signal changes about 10 mV/dB, with a peak-to-peak signal level of up to 685 mV. For lower duty cycles,
the mV/dB slope and peak-to-peak signal level are proportionately less. The signal at BBOUT is riding on a
1.1 Vdc value that varies somewhat with supply voltage and temperature, so it should be coupled through a ca-
pacitor to an external load. A load impedance of 50 K to 500 K in parallel with no more than 10 pF is recom-
mended. When an external data recovery process is used with AGC, BBOUT must be coupled to the external
data recovery process and CMPIN by separate series coupling capacitors. The AGC reset function is driven by
the signal applied to CMPIN. When the receiver is in power-down (sleep) mode, the output impedance of this pin
becomes very high, preserving the charge on the coupling capacitor.
6
CMPIN
This pin is the input to the internal data slicers. It is driven from BBOUT through a coupling capacitor. The input
impedance of this pin is 70 K to 100 K.
7
RXDATA
RXDATA is the receiver data output pin. This pin will drive a 10 pF, 500 K parallel load. The peak current available
from this pin increases with the receiver low-pass filter cutoff frequency. In the power-down (sleep) mode, this pin
becomes high impedance. If required, a 1000 K pull-up or pull-down resistor can be used to establish a definite
logic state when this pin is high impedance. If a pull-up resistor is used, the positive supply end should be con-
nected to a voltage no greater than Vcc + 200 mV.
8
NC
This pin may be left unconnected or may be grounded.
9
LPFADJ
This pin is the receiver low-pass filter bandwidth adjust. The filter bandwidth is set by a resistor R
LPF
between this
pin and ground. The resistor value can range from 330 K to 820 ohms, providing a filter 3 dB bandwidth f
LPF
from
4.5 kHz to 1.8 MHz. The resistor value is determined by:
R
LPF
= 1445/ f
LPF
, where R
LPF
is in kilohms, and f
LPF
is in kHz
A ±5% resistor should be used to set the filter bandwidth. This will provide a 3 dB filter bandwidth between f
LPF
and 1.3* f
LPF
with variations in supply voltage, temperature, etc. The filter provides a three-pole, 0.05 degree
equiripple phase response. The peak drive current available from RXDATA increases in proportion to the filter
bandwidth setting.
10
GND2
GND2 is an IC ground pin. It should be connected to GND1 by a short, low inductance trace.
11
RREF
RREF is the external reference resistor pin. A 100 K reference resistor is connected between this pin and ground.
A ±1% resistor tolerance is recommended. It is important to keep the total capacitance between ground, Vcc and
this node to less than 5 pF to maintain current source stability. If THLD1 and/or THDL2 are connected to RREF
through resistor values less that 1.5 K, their node capacitance must be added to the RREF node capacitance and
the total should not exceed 5 pF.
12
NC
This pin shouild be left unconnected.
13
THLD1
The THLD1 pin sets the threshold for the standard data slicer (DS1) through a resistor R
TH1
to RREF. The thresh-
old is increased by increasing the resistor value. Connecting this pin directly to RREF provides zero threshold.
The acceptable range for the resistor is 0 to 100 K, providing a THLD1 range of 0 to 90 mV. The resistor value is
given by:
R
TH1
= 1.11*V, where R
TH1
is in kilohms and the threshold V is in mV
A ±1% resistor tolerance is recommended for the THLD1 resistor.
8
Pin Descriptions
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